Debugging SoCs Can Be Complicated

There’s nothing worse than thinking you’re close to the finish line of your system-on-a-chip (SOC)…

PCIe Gen6 verification – the PCI Express generation comes of age

Billions of us today – regardless of which Generation we belong to, Gen-X, Gen-Z, Millenials,…

Getting Started with Questa Memory Verification IP

By Chris Spear & Kamlesh Mulchandani  Introduction The best way to create a System on…

Getting Started with Questa Verification IP for Protocols

The best way to create a System on a Chip is with design IP: blocks…

The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

In EDA, the word “simulation” is used everywhere: there is RTL and gate level simulation,…

No to Know VIP – Validated!

We have talked about how one can go from ‘No to Know VIP’ in my…

Verification Horizons: The DAC 2015 Issue

If you were not one of the 100’s of visitors to the Verification Academy booth…

20 Years Ago – 10 Years Ago – Tomorrow (DAC)

It is always good to pause to recognize the companies and individuals with whom we…

Even More UVM Debug in Questa 10.2

We’re really excited about the recent Questa 10.2 release, and I’m sure you’ll be just…