Siemens EDA VIP at Flash Memory Summit

Come and see what Siemens EDA’s Verification IP experts are talking about at the Flash Memory Summit event. This annual…

Debugging SoCs Can Be Complicated

There’s nothing worse than thinking you’re close to the finish line of your system-on-a-chip (SOC) design then, just as you…

PCIe® Gen6 verification – the PCI Express® generation comes of age

Billions of us today – regardless of which Generation we belong to, Gen-X, Gen-Z, Millenials, Generation-Alpha – use PCI Express®…

Getting Started with Questa Memory Verification IP

By Chris Spear & Kamlesh Mulchandani  Introduction The best way to create a System on a Chip is with design…

Getting Started with Questa Verification IP for Protocols

The best way to create a System on a Chip is with design IP: blocks that perform common functions such…

SystemVerilog Multidimensional Arrays

You asked and I listened Thank you everyone who registered and attended my webinar on SystemVerilog arrays. There were many…

The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

In EDA, the word “simulation” is used everywhere: there is RTL and gate level simulation, analog simulation, RF simulation, and…

No to Know VIP – Validated!

No to Know VIP – Validated!

We have talked about how one can go from ‘No to Know VIP’ in my 3 part series and how…

Verification Horizons: The DAC 2015 Issue

Verification Horizons: The DAC 2015 Issue

If you were not one of the 100’s of visitors to the Verification Academy booth at DAC 2015 and missed…