PCIe Gen6 verification – the PCI Express generation comes of age

Billions of us today – regardless of which Generation we belong to, Gen-X, Gen-Z, Millenials, Generation-Alpha – use PCI Express® technology in its various iterations, in our electronic devices and in the datacenter with every compute cloud interaction we make. Those of us who are chip makers and verification experts, need to keep up with today’s and tomorrow’s advances in this key technology. Let’s talk about PCIe Gen6 verification.

PCI Express is one of the most successful standardization efforts and data transfer protocols in our history – comparable to ethernet in importance and reach in the industry, although addressing the challenge of short reach, high bandwidth board level and chip to chip data exchange.

PCI-SIG logo

Since the original PCIe at 2GB speed specification was released back in 2003, there has been regular advances in the specification, the technology, and the transfer speed with each iteration. Now PCIe Gen4 is widely adopted in ubiqutous computing devices, with 16G transfer speeds, and in the datacenter, PCIe Gen5 with 32G transfer speeds and related capabilities such as support for CXL (Compute Express Link) coherency, powers the cloud computing resources we all use with our personal devices and the internet of things.

This year, Gen6 is released which again doubles the performance to 64G transfer rates. It uses PAM4 modulation – similar to GDDR6X and Infiniband protocols. And it uses Flow Control Units (or FLITS) as the unit of communication for efficient, low latency communication and coherency. It is so fast, that it needs Forward Error Correction in addition to the normal CRC error detection and retry protections.

Things are about to get even more complex across the backplane.

PCIe is a complex protocol with Verification challenges

Verification teams working with advanced PCI Express protocol in their blocks or SoCs look for Verification IP solutions to solve the problem – this is the effective way to bring PCIe expertise into your team, and lower your testbench integration and bringup costs considerably.

PCIe link training state machine
PCIe link training state machine

You have a need for predictable confidence that can only come from a robust, independent verification of these complex interfaces. And the solution needs to scale from one design to the next, one PCIe generation to the next. Ours does.

Questa Verification IP for PCIe Gen6 is available today

Siemens Questa VIP for PCIe provides exhaustive verification of PCIe-based IP and SoCs, now including Gen6, and we are working with Early Adopter customers today.

Specifically, for PCI Gen6, Questa VIP provides full support for the latest PCIe 6.0 specification draft 0.7, and PHY Interface for PCI Express (PIPE) version 6.0, in Root Complex(RC), Root Port(RP), Endpoint (EP), and Retimer devices, including PCIe6 features such as 64G transfer speed, PAM4 signaling, FLIT/non-FLIT TLPs, FLIT retry, DOE, alternate protocol support, margining and training, and the PCIe configuration space with 6.0 extended capabilities.

QVIP – Independent but not Isolated

Questa Verification IP from Siemens EDA is an independent solution – we do not sell Design IP, so our customers trust the rigorous and independent verification we have developed.

But independent does not mean isolated – we work very closely with our design IP partners in the industry to harden our product quality by testing on both sides – in the case of PCIe our partner is PLDA automation, chosen for their long standing leadership in PCIe design IP. We have been working with PLDA for many years around PCIe, and you can read more about our joint activities with them in the recent Siemens Partner Blog “PLDA is at the leading edge with advances in PCIe 5.0 and CXL”. We asked PLDA to comment on challenges and solutions for PCIe6.0 verification:

“Innovative customers attempting to gain a first-mover advantage by adopting the early versions of PCIe Gen 6 need a reliable and comprehensive verification IP platform to validate their designs”, said Stephane Hauradou, CTO of PLDA. “With its long heritage of leadership in PCIe VIP, Questa VIP delivers confidence that the standard is and will continue to be fully supported.”

Here at Siemens EDA we are well positioned to build on that leadership now with PCIe Gen6 as that standard marches towards certification. Let’s take a look at some of the advantages of our solution:

QVIP – Interoperability to suit your EDA flow

Questa Verification IP runs on all SV-compliant simulators and is tested on the latest Questa Sim, Xcelium and VCS versions.

If you have a dual source flow or are migrating between simulators or vendors, Questa VIP provides a stable platform to eliminate extra migration effort.

QVIP – Benefits of Automated VIP configuration

If you are familiar with the challenges of Verification IP and UVM testbenches, you will appreciate Questa VIP advantages.

Typical PCIe 5.0 testbench with PLDA Design IP and Questa Verification IP
Typical PCIe 5.0 testbench with PLDA Design IP and Questa Verification IP

Apart from the independence we already talked about, Questa VIP provides extreme automation with its Configurator app taking care of all the initial code generation and config settings, to get you started with real verification traffic within minutes, not days or weeks.

Independent, Available, Comprehensive, Interoperable, Automated – a winning combination

With PCIe Gen6 – the PCI Express generation comes of age, and Questa VIP solution for PCIe6 is ready to provide chip design verification teams with the confidence needed to embrace it and bring it to market.

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