Thought Leadership

Learn About the Security-critical CMA/SPDM, DOE, IDE, and TDISP elements of the PCIe protocol at the 2024 PCI SIG DevCon

By Joe Hupcey III

The Peripheral Component Interconnect Express (PCIe®) protocol is incredibly feature rich; so much so that even experienced engineers can struggle to keep up with the latest enhancements and capabilities. Hence, the “PCI SIG” standards organization holds an annual conference for D&V engineers to learn directly from the industry’s PCIe experts via technical training sessions; sharing best practices to ultimately improve product roll-out and interoperability. My colleagues in the Avery Verification IP R&D group are among these experts that contribute their time to the development of this standard in general, and they are presenting two technical papers at the annual PCI SIC DevCon next week – June 12-13 at the Santa Clara Convention Center.

First, let me define the acronyms for the PCIe protocol features their talks will be covering:

SPDM — Security Protocol and Data Model: Enables system hardware components such as PCIe cards, NVMe drives, etc. to have their identity authenticated and their integrity verified.

CMA — Component Measurement and Authentication: Defines how SPDM is applied to PCIe/CXL systems.

DOE — Data Object Exchange: A specification for data object transport over different interconnects.

IDE — Integrity and Data Encryption: a schema for real-time encryption of data transiting a PCIe data bus, which included capabilities to detect whether the data has been tampered with. Without the real-time encryption provided by IDE, hackers could modify the data flowing in the PCIe bus – something that would be difficult, if not impossible to detect.

TDISP — TEE Device Interface Security Protocol: An architecture for trusted I/O virtualization providing the following functions: 1. Establishing a trust relationship between a TVM and a device. 2. Securing the interconnect between the host and device. 3. Attach and detach a TDI to a TVM in a trusted manner.

And here are the corresponding presentations to look for in the program’s agenda:

Demystifying Verification Challenges of TDISP

Wednesday, June 12 | 3:30 PM – 4:30 PM PT

This session addresses the verification challenges associated with TDISP, and proposes methods to simplify them. TDISP design requirements – and the associated verification plan – needs to include:
1.    Establishing a trust relationship between a TVM and the device.
2.    Securing the PCIe data path between the host and TDI to prevent traffic interception or masquerading on the PCIe fabric.
3.    Securing confidential data of TDI from device controls available to host drivers

Speaker: Tufail Ansari

Tufail Ansari is working as Member Consulting Staff in Avery Verification IP team of Siemens EDA. He has completed his B.Tech in Electronics and Communication Engineering from Delhi Technological University. He has 7 years of working experience in PCIe Gen4, 5, 6 VIPs and working in PCIe security feature from past 3 years.

Implementation of CMA/SPDM for PCI IDE Security

Thursday, June 13 | 1:30 PM – 2:30 PM PT

This paper elaborates how to implement the Security Protocol and Data Model (SPDM) flow using Data Object Exchange (DOE) for PCIe. Specifically, we review these requirements of SPDM:
1.    Provide a robust method to securely exchange keys between devices, which is necessary for encrypting TLPs.
2.    Prevent hackers from intercepting data by encrypting IDE-KM and TDISP packets over an unsecured DOE channel.

Speaker: Suprio Biswas

Suprio Biswas is working as Lead Member Technical Staff in Avery Verification IP team of Siemens EDA. He has completed his B.Tech in Electronics and Communication Engineering from Netaji Subhas Institute of Technology. He has 4 years of working experience in PCIe Gen5 and 6 VIPs.

We also welcome you to come by our booth to meet with our presenters and our other experts at the show.

Hope to see you there!

Joe Hupcey III,
for the Questa Verification Team

P.S. For completeness sake, the above capabilities are also part of the Compute Express Link (CXL) protocol; and thus the techniques in the cited papers apply to CXL designs as well.

Reference Links

1 – How Formal Techniques Can Keep Hackers from Driving You into a Ditch, Part 1 of 2

2 – How Formal Techniques Can Keep Hackers from Driving You into a Ditch, Part 2 of 2

3 – The PCI SIG 2024 Developers conference home page

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