PCIe Gen6 verification – the PCI Express generation comes of age

Billions of us today – regardless of which Generation we belong to, Gen-X, Gen-Z, Millenials, Generation-Alpha – use PCI Express®…

Getting Started with Questa Verification IP for Protocols

The best way to create a System on a Chip is with design IP: blocks that perform common functions such…

PCIe Gen5: A pathway to address Data Explosion and Emerging Technologies

PCIe Gen5: A pathway to address Data Explosion and Emerging Technologies

As the technology scales or shrinks, there are always some bottlenecks that need to be addressed sometimes it is the…

Design & Verification IP Forum 2017

Design & Verification IP Forum 2017

VIP: Accelerating SoC Design Verification Your SoC designs have grown more complex, not just by the sheer number of transistors…

No to Know VIP – Validated!

No to Know VIP – Validated!

We have talked about how one can go from ‘No to Know VIP’ in my 3 part series and how…

No to Know VIP – Part 3

No to Know VIP – Part 3

Thus far we have talked about the importance of having a VIP which is easy to connect to the DUT…

No to Know VIP – Part 2

No to Know VIP – Part 2

Continuing on our journey on what is needed to get to productive verification with VIP, the first step is to…

No to Know VIP

No to Know VIP

In a recent post on deepchip.com John Cooley wrote about “Who Knew VIP?”. In addition, Mark Olen wrote about this…