Design & Verification IP Forum 2017

VIP: Accelerating SoC Design Verification

Your SoC designs have grown more complex, not just by the sheer number of transistors that can be packed into one design, but the emergence of different interconnect methods you must use to connect chip internals and to connect to the outside world.  With each of these interconnect methods, design IP blocks support a faster SoC design process.  However, being an expert on each of the interconnect methods or protocols is not likely leading to protracted SoC verification schedules, reduced design productivity and exposing your designs to bugs that might only be found when in use by the end consumer.

These complex industry standard interfaces can be more rapidly verified in your SoC design with the use of Verification IP (VIP).  You will still need to understand the specific protocols, but when VIP is used you improve design quality and reduce verification time which allows you to hit aggressive time-to-market goals.

To foster industry discussion and share best practices we invite you to the Silicon Valley Design & Verification IP Forum 2017.  The forum brings DIP and VIP designers, integrators and partners together to learn the latest in IP-driven verification trends and solutions.  The forum will have presentations on numerous protocols include MIPI CSI-2, USB 3.1, PCIe Gen 4, DDR & Flash memory and IEEE 802.3 Ethernet PHY.

The day will be full of presentation from those protocol experts and will start with an opening keynote from Mentor’s verification chief scientist, Harry Foster. Harry will explore “Conquering the New IP Economy” in his keynote.  Several of our Questa Vanguard Partners who supply design IP will also be present to show how all this works together to accelerate SoC design verification closure.

Silicon Valley Design & Verification IP Forum 2017 Details

Date: May 9, 2017
Time: 8:30 a.m. – 4:15 p.m. PT
Location: San Jose, CA USA
Register: Click here.

The event is free of charge to qualified registrants and includes lunch.  The lunch keynote will be presented by Niraj Mathur, VP High Speed Interface Products, Rambus.  Niraj will share is 20 years of experience in advanced SoC & IP design, verification, software and cross-functional, global engineering team challenges.

I look forward to seeing your there!

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