PCIe Gen5: A pathway to address Data Explosion and Emerging Technologies

As the technology scales or shrinks, there are always some bottlenecks that need to be…

Mitigating Security Risks When Designing with 3rd-Party Silicon IP

Accellera DAC Panel to Discuss There is probably not one embedded system that is not…

Design & Verification IP Forum 2017

VIP: Accelerating SoC Design Verification Your SoC designs have grown more complex, not just by…

How Any Verification Engineer Can Quickly Create a Complex Testbench

Over the past decade or so, the state of the art in design verification has…

UVM Forum 2015 LIVE!

Verification Academy Brings “UVM Live” to the Santa Clara Convention Center For everyone involved in…

No to Know VIP

In a recent post on deepchip.com John Cooley wrote about “Who Knew VIP?”. In addition,…

Who Knew VIP?

“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by…

Preparing for the Perfect Storm with New-School Verification Techniques

Between 2006 and 2014, the average number of IPs integrated into an advanced SoC increased…

UVM: Joint Statement Issued by Mentor, Cadence & Synopsys

DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys The full statement…