The Many Flavors of Equivalence Checking: Part 3, How SLEC Brings Automated, Exhaustive Formal Analysis to Low Power Clock Gating Verification

[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and…

Part 11: The 2018 Wilson Research Group Functional Verification Study

ASIC/IC Low Power Trends This blog is a continuation of a series of blogs related…

Prologue: The 2018 Wilson Research Group Functional Verification Study

This is the first in a sequence of blogs that presents the findings from our…

Upcoming Wilson Research Group Functional Verification Study Web Seminar

About every two years, Mentor, A Siemens Business, commissions Wilson Research Group to conduct a…

See You at DVCon U.S. 2018!

We hope to see you at DVCon U.S. 2018.  Mentor will showcase 17 papers and…

How To Connect Your Testbench to Your Low Power UPF Models

Face facts: power supply nets are now effectively functional nets, but they are typically not…

Part 11: The 2016 Wilson Research Group Functional Verification Study

ASIC/IC Power Trends This blog is a continuation of a series of blogs related to…

3 Things About UPF 3.0 You Need to Know Now

UPF 3.0 has been an official IEEE standard since January, but its most valuable capabilities…

DVCon India 2016–Outstanding Program Awaits

A great technical program awaits you for DVCon India 2016!  The DVCon India Steering Committee…