Verification Academy 2026 webinar round-up

It’s hard to believe, but we’re already almost halfway through 2026! Time flies when you’re innovating, and here at Siemens,…

BUGGED OUT PODCAST

Introducing BUGGED OUT — A new bite-sized podcast for verification engineers

BUGGED OUT Podcast

Accellera announces fee-free availability of IEEE Std. 1801™-2024

Accellera announced the latest revision of the IEEE Standard for Design and Verification of Low-Power Energy-Aware Electronic Systems, also known…

Part 11: The 2022 Wilson Research Group Functional Verification Study

IC/ASIC Power Management Trends This blog is a continuation of a series of blogs related to the 2022 Wilson Research…

Part 11: The 2020 Wilson Research Group Functional Verification Study

IC/ASIC Power Management Trends This blog is a continuation of a series of blogs related to the 2020 Wilson Research…

The Many Flavors of Equivalence Checking: Part 3, How SLEC Brings Automated, Exhaustive Formal Analysis to Low Power Clock Gating Verification

[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and SLEC, and Part 2 describes…

Part 11: The 2018 Wilson Research Group Functional Verification Study

Part 11: The 2018 Wilson Research Group Functional Verification Study

IC/ASIC Power Management Trends This blog is a continuation of a series of blogs related to the 2018 Wilson Research…

Upcoming Wilson Research Group Functional Verification Study Web Seminar

Upcoming Wilson Research Group Functional Verification Study Web Seminar

About every two years, Mentor, A Siemens Business, commissions Wilson Research Group to conduct a broad, vendor-independent study of design…

See You at DVCon U.S. 2018!

See You at DVCon U.S. 2018!

We hope to see you at DVCon U.S. 2018.  Mentor will showcase 17 papers and posters during the conference on…