What happens in Vegas…is happening in the Verification Academy and Mentor booths!

It’s been 18 years since DAC last visited Las Vegas, and a lot has happened…

Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers

[Preface: we are presenting a paper on this topic at the upcoming SEE/MAPLD conference, May…

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

[Preface: at the upcoming DVCon 2018 in San Jose, poster 4.12 addresses some of the…

See You at DVCon U.S. 2018!

We hope to see you at DVCon U.S. 2018.  Mentor will showcase 17 papers and…

Are You Struggling to Reach Timing Closure with Your Low Power Design – You May Have CDC Problems!

First, if you were brought here by a desperate Google search for “timing closure tricks…

NEW Formal & CDC Courses on Verification Academy

Do you have a really tough verification problem – one that takes seemingly forever for…

ASYNC 2015: The Most Important CDC Conference You’ve Never Heard Of

Because Clock Domain Crossing (CDC) verification has been around for well over a decade, it’s…

Static Verification

After spending years verifying ASICs with dynamic simulation, I started working on static verification 10…