Accellera Day at DVCon U.S. 2024

DVCon U.S. 2024 will be a week packed with paper sessions, tutorials, panels, keynotes and more on the latest in…

Pro Tip: Planning to Land Your Spacecraft on Mars? You Will Need CDC, RDC, and Formal Property Checking

If you are an engineer at one of the growing number of entities looking to land a spacecraft on Mars…

Cooking with a non-stick pan

Non-stick surfaces and RTL design

How to keep RTL designers from costing their co-workers dinners and bedtimes in the most efficient way possible.

What happens in Vegas…is happening in the Verification Academy and Mentor booths!

What happens in Vegas…is happening in the Verification Academy and Mentor booths!

It’s been 18 years since DAC last visited Las Vegas, and a lot has happened in verification during this period….

Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers

Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers

[Preface: we are presenting a paper on this topic at the upcoming SEE/MAPLD conference, May 21-24, 2018 in La Jolla,…

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

[Preface: at the upcoming DVCon 2018 in San Jose, poster 4.12 addresses some of the issues raised below, as well…

See You at DVCon U.S. 2018!

See You at DVCon U.S. 2018!

We hope to see you at DVCon U.S. 2018.  Mentor will showcase 17 papers and posters during the conference on…

Are You Struggling to Reach Timing Closure with Your Low Power Design – You May Have CDC Problems!

Are You Struggling to Reach Timing Closure with Your Low Power Design – You May Have CDC Problems!

First, if you were brought here by a desperate Google search for “timing closure tricks STA RTL” as your tape…

NEW Formal & CDC Courses on Verification Academy

NEW Formal & CDC Courses on Verification Academy

Do you have a really tough verification problem – one that takes seemingly forever for a testbench simulation to solve…