Thought Leadership

What happens in Vegas…is happening in the Verification Academy and Mentor booths!

By Harry Foster

It’s been 18 years since DAC last visited Las Vegas, and a lot has happened in verification during this period. To keep up with all these changes in verification we have created the Verification Academy with the goal of providing the skills necessary to mature an organization’s advanced functional verification processes. The Verification Academy has been a key contributor at DAC for the past eight years by providing industry focused technical talks directly to the exhibit floor of DAC.

This year we have invited twenty-one speakers to present in the Verification Academy Theater (#617) who will focus on key technical aspects of advanced functional verification, including: AMS, UVM, Coverage, Assertion-Based Verification, Verification Management, CDC, Formal Verification, Acceleration, Requirements Verification, the Portable Test and Stimulus Standard (PSS) and more.

One of our key partners, Cliff Cummings from Sunburst Design, will present an insightful presentation on the future needs of SystemVerilog: What’s Missing and What Should Be Next for SystemVerilog. If you have never heard Cliff speak, you are in for a treat! I consider Cliff “Mr. SystemVerilog,” and in this talk he shares considerations and approaches for enhancing the SystemVerilog language as well as features that he believes should be strongly considered for the next IEEE SystemVerilog Standard.

There are a few additional Verification Academy invited talks I want to highlight:

  • PSS: Is It Revolution or Evolution?
    What if there was a way to adopt the revolutionary PSS innovation incrementally? For example, leveraging existing verification infrastructure, including existing UVM/SV test benches and verification IP, which would enable the benefits of PSS incrementally as the workforce gets up to speed. Come hear Tom Fitzpatrick present on how reuse can be the evolution that enables the PSS revolution.
  • RISC-V Core & SoC Compliance, Verification, Customization
    In this invited talk, Larry Lapides from Imperas Software Ltd. will discuss how the open instruction set architecture of RISC-V provides significant innovation freedoms (such as easy addition of custom instructions and extensions), but also puts more demands on design teams in terms of compliance checking and verification of the cores. This presentation will discuss the balancing act for RISC-V, development and go through flows, tools and models for compliance, verification and adding custom instructions using various case studies.
  • Mixed-Signal Challenges for Digitally Assisted nm-CMOS High Speed SerDes Targeted for 5G and Automotive Applications
    In mixed signal designs, digital circuits severely slow down the SPICE simulation throughput as they consist of a large number of transistors – much larger than their analog counterparts. This talk introduces a methodology to improve mixed-signal simulation throughput by defining these digital circuits in high-level abstractions during simulations of the whole system.
  • Methodology to Debug Real Number Model Boundary Scenarios using Symphony & Questa Visualizer Debug Environment
    Real Number Models (RNM) empowers verification engineers to describe an analog block as a discrete floating point model, and enable it to simulate in a digital solver at near-digital simulation speeds. In this talk you will learn how to take advantage of Symphony and Questa Visualizer to debug RNM boundary scenarios in case of functional failures.

For a complete listing of invited talks visit our Verification Academy at DAC 2019 webpage where you can register for a specific session.

In addition to the Verification Academy talks, I would like to highlight an excellent line up of AMS sessions in the Mentor booth (#334):

  • Addressing nm Analog/Mixed-Signal Circuit Verification with Mentor’s Analog FastSPICE (AFS) Platform
    Design activity surrounding 5nm node is quickly ramping up, resulting in increasingly complex design issues that must be overcome. In this session, learn how Mentor’s Analog FastSPICE® address AMS Circuit Verification challenges at 5nm and beyond.
  • Solido ML Characterization Suite Demo
    Library characterization performed by “brute-force” requires millions to billions of SPICE simulations, and weeks to months of runtime. This live demo shows how MLChar Generator produces production-accurate .LIBs at new PVT corners in minutes.
  • Solido Variation Designer Suite Demo
    At lower nodes, increasing verification coverage and improving design quality is significantly important for fast TTM. This demo will cover the latest capabilities in Solido Variation Designer and also introduce Solido’s new High-Sigma Verifier, a next-generation tool with algorithmic breakthroughs that make high-sigma verification faster and easier than ever before.
  • Solving Today’s Mixed-Signal Verification Challenges with Symphony
    This session introduces Mentor’s new Symphony Mixed-Signal Platform, where you will learn about its performance advantages, intuitive use-model and breakthrough debug capabilities that helps achieve first silicon success across several mixed-signal IC applications

At the Mentor booth and Verification Academy Theater we have packed each day full of exciting activities focused on the latest in cutting-edge technologies. Visit our websites to find your favorite Mentor experts and sessions—whether in our Mentor booth (#334), Verification Academy Theater (#617) or in the conference.

I look forward to seeing you at the 56th Design Automation Conference in Las Vegas June 2-6!

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This article first appeared on the Siemens Digital Industries Software blog at