An image of an IC on a PCB

Verification IP: Why design teams buy instead of build

When we say verification IP, we mean pre-built verification solutions for standards-based peripheral interconnect interfaces and memories.

DVClub Austin

Join Me at DVClub Austin — May 20, 2026

The End of Orthogonalization: Why Verification Is Entering a New Era The semiconductor industry is entering one of the biggest…

An illustration of a chip next to a computer screen representing an engineer doing formal verification

Beyond simulation: Unlocking absolute certainty in hardware design with formal verification

Explore how formal verification is revolutionizing hardware design by offering not just confidence, but absolute certainty in design’s correctness.

BUGGED OUT PODCAST

Introducing BUGGED OUT — A new bite-sized podcast for verification engineers

BUGGED OUT Podcast

Functional Verification Insights with Abhi Kolpekwar

Functional verification insights: a conversation with Abhi Kolpekwar

Over the years, I’ve had the privilege of sharing industry data and analysis through the Siemens EDA & Wilson Research Group…

GOMACTech 2025 Preview: FPGA Safety and Security Policy Compliance via HDL-to-Bitstream Equivalence Checking (Session 43.5)

Security and safety policies across domains such as embedded security, defense safety, and automotive safety have been updated to require…

DVCon 2025: A must for hardware design and verification engineers

I’ve attended every DVCon US conference since its inception, over 30 years ago. I’ve also given keynotes at DVCon India….

Breaking the Bottleneck: A Smarter Approach to Semiconductor Verification

The semiconductor industry is facing a new reality: traditional verification methods can no longer keep pace with the rapid evolution…

osmosis 2024

osmosis 2024 – pushing the boundaries of formal verification

Thank you for making osmosis 2024 a success! The annual osmosis 2024 event has once again proved to be a…