Siemens EDA at FMS 2025 – Shaping the Future of Memory and Storage

We’re excited to connect with fellow innovators, engineers, and industry leaders at FMS 2025. Whether you’re attending our sessions or stopping by Booth #1140, we look forward to sharing the latest technical advancements in verification IP, system-level validation, and memory and interconnect technologies.

Industrial-Grade AI in EDA: From Promise to Practice — A Siemens Panel at DAC 2025

Industrial-Grade AI in EDA

First-Silicon Success

Generative AI: The Hype, The Hope, The Hard Truths — And the Debate at DAC

The semiconductor industry is no stranger to bold claims. But few topics today spark more debate — or more genuine…

From Rule-Based Beginnings to AI-Driven Design: Tracing the Evolution of AI in EDA

As we gear up for the 62nd Design Automation Conference (DAC) in San Francisco, one of the most anticipated events…

User2User

Closing the Gap in Software Skills for Verification Engineers

I’m excited to announce next month’s U2U (User-to-User) meeting, followed by a crucial technical training session that no hardware verification…

Accellera announces fee-free availability of IEEE Std. 1801™-2024

Accellera announced the latest revision of the IEEE Standard for Design and Verification of Low-Power Energy-Aware Electronic Systems, also known…

GOMACTech 2025 Preview: Improving Productivity with Parallel Simulation (Poster P.9)

Field Programmable Gate Arrays (FPGAs) continue to be a critical part of system designs, and their complexity grows as new…

GOMACTech 2025 Preview: FPGA Safety and Security Policy Compliance via HDL-to-Bitstream Equivalence Checking (Session 43.5)

Security and safety policies across domains such as embedded security, defense safety, and automotive safety have been updated to require…

Backpacking Yosemite Aug 2024

Got Coverage?

Welcome to 2025. What happened?! “Coverage” in August in Yosemite backpacking has a different meaning. In August? Snow? Lots of…