Latest posts

Pool of parameterized handles in SystemVerilog

Groups of Class Specializations in SystemVerilog

Introduction In a previous post, I said that in SystemVerilog, once you specialize a class, you can not make a…

DVConUS 2023 Verification Horizons is Out

Some of you may have wondered for the past few years why we chose to use the name Verification Horizons…

ML for Verification

Big Data for Verification – Inspiration from Large Language Models

The importance of verification data learned from training Large Language Models. In DVCon will share an overview of ML applications in verification and . present VIQ tutorial on how data can empower verification, with demos of existing ML applications.

3 Ways DVCon US 2023 is Going to be Different This Year

1 – The Tuesday keynote For the first F2F/IRL DVCon since 2020, the Steering Committee wanted a fresh alternative to…

DVCon U.S. 2023: Expanded Accellera content

DVCon U.S. 2023 will be full of opportunities to learn about advances in design and verification technology as it returns…

To UVM Config or Not at DVCON US – Can chatGPT do it better?

It’s all about speed and productivity for Verification Engineers and Designers. And of course, the UVM is the ticket, and…

ML for Verification

Unleashing the Power of Verification Data with Machine Learning

Importance of data in verification can never be underestimated, start building data assets and unlock the value with Machine Learning.

Re-imagining requirements management for safety-critical projects

Project teams face a host of challenges when developing semiconductors compliant to a safety critical market. Whether that’s ISO 26262…

The UVM string-based Factory can print base and derived objects

The UVM Factory Revealed, Part 2

Introduction This is a follow up to last week’s high-level post on the UVM Factory. Now let’s get technical! Here…