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ISO 26262

ISO 26262…the tale of Transient and Permanent Faults

Introduction Are you designing to the ISO 26262 standard and trying to decide if your design is safe from random…

Part 2: The 2022 Wilson Research Group Functional Verification Study

In my previous blog, I present FPGA design trends identified in the 2022 Wilson Research Group Functional Verification Study to…

Three ice cream cones, vanilla, chocolate, and strawberry

Does Your UVM Flavor Have Sprinkles?

Introduction UVM is a standard, so that means that every company writes their testbenches the same, universally interchangeable, right? Not…

osmosis 2022 - December 8, 2022 in Munich

Osmosis – our annual event for formal verification users – is back F2F this December 8, 2022!

Attention anyone interested in Formal Verification: after a hiatus due to you-know-what, osmosis is back in-person this coming December 8…

A pool of specialized classes

Dig a Pool of Specialized SystemVerilog Classes

Introduction SystemVerilog classes are a great way to encapsulate both variables and the routines that operates on them. What if…

Part 1: The 2022 Wilson Research Group Functional Verification Study

In my previous blog, I introduced the 2022 Wilson Research Group Functional Verification Study (click here). The objective of my previous…

Prologue: The 2022 Wilson Research Group Functional Verification Study

This is the first in a sequence of blogs that presents the findings from our new 2022 Wilson Research Group…

My Day At The Beach - Early

UVM Testbench Debug – A Day At The Beach – Right?

Some people think UVM Testbench Debug is a drag. But really, it depends. I think it’s a day at the…

Implicit handle: this

SystemVerilog: Implicit handles

Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some…