Latest Posts

Debugging SoCs Can Be Complicated

There’s nothing worse than thinking you’re close to the finish line of your system-on-a-chip (SOC) design then, just as you…

Siemens EDA at the 58th Design Automation Conference

Welcome to the 58th Design Automation Conference, and welcome back to the beautiful city by the bay—San Francisco! The 58th…

TLM 1.0 in pyuvm

This blog post is part of a continuing series discussing Python as a verification language. You can find links to…

Design Linting for ISO 26262

ISO 26262 remains the state of the art standard guiding the development of electronic and electronic systems destined for the…

How Can You Say That Formal Verification Is Exhaustive?

As a companion to my previous post on Learn Formal the Easy Way, allow me to explain what are often…

Stop

Leave the House With a Clean Design

Wouldn’t it be great if there were something that would stop you from leaving the house wearing mismatched clothes – I mean without a clean design?

Python and the UVM

In our previous two posts in this series on Python as a verification language, we examined Python coroutines and using…

Verification Horizons | September 2021

The September Verification Horizons is Now Online!

I’m really excited to share with you a very special issue of the Verification Horizons newsletter for September, 2021. The…

Why Is My Coverage The Way It Is?

Coverage is as Coverage does Writing coverage is an art. At least it is a skill which takes imagination, practice…