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Deploying Formal in a DO-254 Program

The primary focus of DO-254, referred to as ED-80 in Europe, is hardware reliability of airborne electronic hardware. DO-254 is…

Base and derived classes and their handles

Class Variables and Assignments in SystemVerilog

Introduction Good OOP style says you should start your project with a common base class (or several). When you want…

Qrun-ing Optimized Build Flows in Questasim

Qrun-ing with Questasim For Questasim users, qrun will be a welcome surprise. Admittedly, I’ve never been a huge fan of…

Runtime checks with the $cast() method

Introduction Verilog was always known for its lack of type checking, treating everything as just bits strung together into vectors…

Verification Class Categories

Introduction What can you describe with Object-Oriented Programming? When I learned OOP, we had cute classes like animals, cars, and…

SystemVerilog Class Variables and Objects

Introduction How can you visualize the relationship between classes and objects in SystemVerilog? This is the first post in a…

Verification Academy UVM Video Courses Updated!

Two significant milestones were reached earlier this year. The first is that the Universal Verification Methodology (UVM) celebrated its 10-year…

Accellera FuSa WG: White paper released!

The Accellera Functional Safety Working Group was formed to address critical industry challenges suppliers, systems integrators and manufacturers face delivering…

Explanation of “Verification” in a DO-254 program

Often times, I’m asked to define what verification activities are required for a DO-254 program. For those experienced in a…