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Asking better questions on the Verification Academy Forums with EDAPlayground

The forums on the Verification Academy have been around for about a decade (even longer…

SystemVerilog Static Methods

Introduction In my last post, you learned how to create a class with a static…

Mastering Today’s Emerging Functional Safety Workflows

Last week the Verification Academy announced the new Introduction to ISO 26262 “Road vehicles –…

Navigating the Road to Functional Safety

One example of increasing requirements that are contributing to growing electronic system complexity relates to…

SystemVerilog Classes with Static Properties

Introduction One of the advantages of creating your testbenches with Object Oriented Programming, as opposed…

Tools In A Methodology Toolbox

To understand how techniques fit together as part of a comprehensive verification methodology, we’re mapping…

SystemVerilog Parameterized Classes

SystemVerilog allows you to create modules and classes that are parameterized. This makes them more…

How to Increase UVM Code Generation Productivity

I think most project teams agree that there is a lot of benefit in adopting…

Verification Methodology Reset

Discussion around verification methodologies have been going on for a couple decades. It started back…