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SystemVerilog Multidimensional Arrays

You asked and I listened Thank you everyone who registered and attended my webinar on…

Getting Organized with SystemVerilog Arrays

SystemVerilog has many ways to store your data. Vectors, arrays, structures, classes, and probably several…

PCIe Gen5: A pathway to address Data Explosion and Emerging Technologies

As the technology scales or shrinks, there are always some bottlenecks that need to be…

The Many Flavors of Equivalence Checking: Part 4, How SLEC Brings Automated, Exhaustive Formal Analysis to Safety Mechanism Verification

[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and…

Exciting Webinar on Portable Stimulus Now Posted

[Updated 5/27/2020] The webinar went off without a hitch and is now available for viewing…

Methodology by Example – 6 Approaches to Verification

This blog is an exciting next step – exciting for me at least! – that…

New Webinar Series: What’s New in Mentor Functional Verification

Just like time and the tides, the complexity of electronic systems, and the need to…

UVM Configuration DB Guidelines

Introduction My previous blog posts were on static and parameterized classes to get you ready…

The Ideal Verification Timeline

Our discussion around building integrated verification methodologies started with where techniques apply to design by…