Fix first, finish faster!

By James Paris

A few years ago, I came across some plans to build a simple bookshelf that would fit perfectly in my home. I already had the required tools, so I went out and bought the materials, then got to work. Cutting the lumber to length, assembling the bookcase using glue and my nailgun, filling any gaps with wood filler, and sanding everything down went quickly and smoothly. In no time, I was ready to paint! During my final inspection, I did notice some of the gaps were not filled all the way, and there were drips of glue on the back that hadn’t been completely sanded down. In my impatience to finish, I thought surely those minor imperfections wouldn’t show up after painting, so I picked up the paintbrush and applied the first coat. I was simultaneously impressed and depressed by how much a coat of paint seemed to magnify those seemingly small issues! After waiting for the paint to dry completely, I had to go through a few more iterations of sanding and filling before applying two more coats of paint. It would have been much easier and taken a lot less time to fix all those flaws before I started painting.

What did I learn? Paint enhances the final appearance of a properly prepared surface, but it also highlights any defects. Also, it’s easier to fix those defects before you’ve slapped a layer or two of paint over everything.

Similarly, when you’re working on verification of a dirty design with incomplete data, you can run your finely-tuned Calibre foundry signoff rule deck, but you probably won’t get the end result you are expecting. And it’s going to be a lot harder and take a lot more time to get to the root cause of even basic design errors because you’ve got millions of results to sort through.

Want to make sure you “sand off” all those rough spots in your design before running signoff? One preemptive strategy for verifying dirty data and incomplete designs is to define a targeted set of checks based on design LEF/DEF data that you can use to validate specific design elements without running your entire foundry rule deck. These custom checks can target basic design errors (like overlapping blocks), or broader systemic errors that can be really hard to fix by the time you get to signoff. Finding and clearing these sorts of errors with a smaller, focused set of checks can not only help reduce your overall verification time, but also improve your productivity.

If you’d like to see some examples of these types of checks, and the process of using them, download a copy of our paper, Custom integrity checks find early IC design implementation errors. Beginning early-stage verification with these types of checks can help you eliminate known design issues and basic layout mistakes before they become deeply entrenched in your design.

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This article first appeared on the Siemens Digital Industries Software blog at