Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs….

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation…

Why Do We Need Assembly Design Kits for Packages?

By John Ferguson and Tarek Ramadan, Mentor Graphics Why do we need assembly design kits…

Design Rule Checking for Silicon Photonics

By Ruping Cao, Mentor Graphics Verifying silicon photonics designs requires new techniques, like equation-based DRC…

Case Studies in Double-Patterning Debug: Part One

By David Abercrombie, Mentor Graphics Multi-patterning errors in P&R layouts can be intricate, and their…

Managing Waivers Throughout the Custom Design Lifecycle

By Srinivas Velivala, Mentor Graphics Custom designer? Learn how you can easily manage DRC waivers…

Custom Layout Designers Need New Tools for New and Expanding Markets

By Srinivas Velivala, Mentor Graphics New debugging capabilities in Calibre RealTime can help shrink your…

Rule Deck Comparison Doesn’t Have to be Difficult

By Saunder Peng Comparing results from different rule decks can be frustrating. Learn how you…

2-5X Productivity Improvement in 14FDSOI Layout Design: STMicroelectronics Experience with Calibre RealTime

By Atul Bhargava and Mehak Malhotra, STMicroelectronics, India and Srinivas Velivala, Mentor Graphics Rather than…