Fix first, finish faster!

By James Paris A few years ago, I came across some plans to build a…

Don’t like standing in lines? Get with the (right) programs!

By John Ferguson For a while, it appeared that the worst of the COVID pandemic…

Custom layout designers…Want to know a secret? You can close DRC faster. A lot faster…

By Srinivas Velivala Design rule checking (DRC) closure is a “tax” that custom layout designers…

Give me my space! Why high voltage and multiple power domain designs need automated context-aware spacing checks

By Sherif Hany and Abdellah Bakhali Regardless of which technology node they’re using, design houses…

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs….

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation…

Why Do We Need Assembly Design Kits for Packages?

By John Ferguson and Tarek Ramadan, Mentor Graphics Why do we need assembly design kits…

Design Rule Checking for Silicon Photonics

By Ruping Cao, Mentor Graphics Verifying silicon photonics designs requires new techniques, like equation-based DRC…

Case Studies in Double-Patterning Debug: Part One

By David Abercrombie, Mentor Graphics Multi-patterning errors in P&R layouts can be intricate, and their…