Mastering parasitic extraction at the 3 nm process node

By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen…

ERC softchk features

StreamliningIC design verification with Calibre® nmLVS Recon™

By Kesmat Shahin As integrated circuits (ICs) become more complex, meeting tapeout schedules has become increasingly challenging. Statistics from industry…

ERC softchk features

The secret superpower of early design verification

By Kesmat Shahin How many times, as you traversed across design stages and ran countless iterations, have you wished that…

Infineon and Siemens collaborate for innovation

By Karen Chow When Infineon needed to select a field solver for the development of their next-generation power semiconductor products,…

Outta my way – electrons coming through!

By Joel Mercier and Karen Chow Ever been in a hurry to get to a meeting, but there were a…

LVS Zero to Hero in 3 Easy Steps

By James Paris When it comes to system-on-chip (SoC) physical verification turnaround-time, layout vs. schematic (LVS) verification can make or…

Does your parasitic extraction work in 5G IC designs?

By Salma Ahmed and Karen Chow The next-generation 5G mobile communication network is a heterogeneous network providing significant performance advantages…

Extracting parasitics from MIM/MOM capacitors doesn’t have to hurt!

By Claudia Relyea and Sandeep Koranne  Analog/RF designers need both the speed of rule-based PEX, as well as the capacity…

Want to know what went on at the TSMC OIP Forum this year? Here’s the inside scoop…

TSMC customers and partners always look forward to the annual TSMC Open Innovation Platform® (OIP) Forums. Here, they get the…