Early circuit verification can get you to tapeout faster…here’s how

For the last few years, it’s been hard to see design teams struggling to meet…

LVS Zero to Hero in 3 Easy Steps

When it comes to system-on-chip (SoC) physical verification turnaround-time, layout vs. schematic (LVS) can make…

Device Pin-Specific Property Extraction For Layout Simulation

By Phil Brooks, Mentor Graphics Can you accurately extract device pin-specific properties without creating phantom…

Electromigration protection requires accurate interconnect modeling

By Karen Chow, Mentor Graphics Electromigration can destroy an IC before its time. Are your…

Reducing Post-Placement Leakage with Stress-Enhanced Fill Cells

By Valeriy Sukharev, Jun-Ho Choy, Armen Kteyan and Henrik Hovsepyan, Mentor Graphics Optimizing power usage…

Parasitic Extraction for Accurate Signal Integrity Analysis at Advanced Nodes

By Karen Chow, Mentor Graphics Signal integrity analysis at advanced nodes requires new and enhanced…

Parasitic extraction for touchscreen designs

By Mohamed ElRefaee, Mentor Graphics Accurate parasitic extraction of touchscreens is essential for ensuring the…

Extraction Challenges Grow in Advanced Nanometer IC Design

By Carey Robertson, Mentor Graphics The Calibre xACT platform is a new type of extraction…

Parasitic Extraction of FinFET-based Memory Cells

By Karen Chow, Mentor Graphics Accurate and efficient FinFET characterization requires a parasitic extraction tool…