Navigating the complex world of resistance extraction for curvilinear shapes in IC designs

By Nada Tarek As integrated circuit (IC) designs continue to push the boundaries of what’s possible, we’re seeing an explosion…

Faster design verification with Calibre nmLVS Recon Compare

By Wael ElManhawy Layout versus schematic (LVS) comparison is a fundamental step in integrated circuit (IC) design verification. It ensures…

Cracking the code: ensuring reliability and performance in IC design with EM/IR analysis

By Karen Chow and Joel Mercier Integrated circuits (ICs) are everywhere, powering everything from washing machines and TVs to medical…

Balancing performance vs. debuggability in LVS circuit verification

By Wael ElManhawy Circuit verification engineers face ever more challenges as semiconductor technology evolves towards smaller process nodes and integrated…

How to verify well layer connectivity with soft checks

By Terry Meeks In the landscape of modern IC chip verification, ensuring the connectivity from diffusion layers to well regions…

Mastering parasitic extraction at the 3 nm process node

By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen…

ERC softchk features

Streamlining IC design verification with Calibre nmLVS Recon

By Kesmat Shahin As integrated circuits (ICs) become more complex, meeting tapeout schedules has become increasingly challenging. Statistics from industry…

ERC softchk features

The secret superpower of early design verification

By Kesmat Shahin How many times, as you traversed across design stages and ran countless iterations, have you wished that…

Infineon and Siemens collaborate for innovation

By Karen Chow When Infineon needed to select a field solver for the development of their next-generation power semiconductor products,…