Does your parasitic extraction work in 5G IC designs?

By Salma Ahmed and Karen Chow The next-generation 5G mobile communication network is a heterogeneous network providing significant performance advantages…

Extracting parasitics from MIM/MOM capacitors doesn’t have to hurt!

By Claudia Relyea and Sandeep Koranne  Analog/RF designers need both the speed of rule-based PEX, as well as the capacity…

Want to know what went on at the TSMC OIP Forum this year? Here’s the inside scoop…

TSMC customers and partners always look forward to the annual TSMC Open Innovation Platform® (OIP) Forums. Here, they get the…

Early circuit verification can get you to tapeout faster…here’s how

For the last few years, it’s been hard to see design teams struggling to meet tapeout schedules caused by increasing…

LVS Zero to Hero in 3 Easy Steps

When it comes to system-on-chip (SoC) physical verification turnaround-time, layout vs. schematic (LVS) can make or break tapeout plans. Working…

Device Pin-Specific Property Extraction For Layout Simulation

Device Pin-Specific Property Extraction For Layout Simulation

By Phil Brooks, Mentor Graphics Can you accurately extract device pin-specific properties without creating phantom nets?  

Electromigration protection requires accurate interconnect modeling

Electromigration protection requires accurate interconnect modeling

By Karen Chow, Mentor Graphics Electromigration can destroy an IC before its time. Are your designs safe?

Reducing Post-Placement Leakage with Stress-Enhanced Fill Cells

Reducing Post-Placement Leakage with Stress-Enhanced Fill Cells

By Valeriy Sukharev, Jun-Ho Choy, Armen Kteyan and Henrik Hovsepyan, Mentor Graphics Optimizing power usage for mobile devices at advanced…

Parasitic Extraction for Accurate Signal Integrity Analysis at Advanced Nodes

Parasitic Extraction for Accurate Signal Integrity Analysis at Advanced Nodes

By Karen Chow, Mentor Graphics Signal integrity analysis at advanced nodes requires new and enhanced parasitic extraction techniques