DRC voltage text annotations: Manually placed texts can be wrong!

By Abdellah Bakhali System-on-chip (SoC) designs often use multiple intellectual property (IP) blocks from multiple IP providers. Each IP provider…

Do you trust the reliability of your 2.5D/3D IC package designs?

By Dina Medhat 2.5D/3D ICs have become an innovative solution for many design and integration challenges. Basic physical verification for…

Reliability checking for memory circuit design doesn’t have to destroy your eyesight!

By Hossam Sarhan Memory blocks contain sensitive analog circuits that are crucial for the proper functionality of the whole design….

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…

Stronger together! Context-aware SPICE simulation combines the strengths of static and dynamic verification for faster, more precise full-chip ESD verification

By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…

Cloud Computing Makes Overnight TAT Attainable

By Matthew Hogan and Derong Yan As we all know, during the final sign-off verifications of full chip system-on-chip (SoC)…

Caution! Avoid detours when improving resistance on ESD paths

By Derong Yan As overall transistor dimensions shrink, integrated circuit (IC) chip designs become more sensitive to the damage caused…

2.5/3D IC designers! Don’t get hung up on latch-up!

By Dina Medhat Latch-up is modeled as a short circuit (low-impedance path) that occurs in an integrated circuit (IC). It…

Don’t hit a roadblock in automotive electronics reliability verification!

The recent surge in used car prices may have you wondering what is driving this upswing, and just how much…