Give me my space! Why high voltage and multiple power domain designs need automated context-aware spacing checks

By Sherif Hany and Abdellah Bakhali Regardless of which technology node they’re using, design houses…

Building a strong reliability foundation with Calibre PERC

By Matthew Hogan How are you handling your reliability verification right now? Custom reliability verification?…

Automated ESD protection verification for 2.5-3D ICs is now a reality

Got the mid-winter blahs? The post-New Year letdown? Looking for something to rev you up?…

Help! I’m not an ESD expert! Reducing ESD verification complexity

By Abdellah Bakhali – Mentor, A Siemens Business If you’re not an ESD expert (and…

Do you have a reliable automated waiver process for reliability verification?

By Dina Medhat – Mentor, A Siemens Business Design rule waivers Maybe a design rule…

A new path for analog design constraints verification

By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for…

Leveraging Reliability-Focused Foundry Rule Decks

By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you…

Interconnect Robustness Depends on Scaling for Reliability Analysis

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness…

Collaborative SoC Verification

By Matthew Hogan, Mentor Graphics The increasing use of SoC designs turns efficient IC design…