A new path for analog design constraints verification

By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for…

Leveraging Reliability-Focused Foundry Rule Decks

By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you…

Interconnect Robustness Depends on Scaling for Reliability Analysis

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness…

Collaborative SoC Verification

By Matthew Hogan, Mentor Graphics The increasing use of SoC designs turns efficient IC design…

Automated Power Model Verification for Analog IPs

By Sierene Aymen and Hartmut Marquardt, Mentor Graphics Eliminating manual work during power intent verification…

An Automated Solution for Voltage-Aware DRC

By Dina Medhat, Mentor Graphics Automated voltage propagation with Calibre PERC makes it easier to…

Electromigration and IC Reliability Risk

By Dina Medhat, Mentor Graphics Gradual damage from electromigration can affect product performance and reduce…

LEF/DEF IO Ring Check Automation

By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning…

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks…