PERC

Leveraging Reliability-Focused Foundry Rule Decks

Leveraging Reliability-Focused Foundry Rule Decks

August 12, 2016

By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you correct reliability issues while they…

By Design With Calibre
4 MIN READ
Interconnect Robustness Depends on Scaling for Reliability Analysis

Interconnect Robustness Depends on Scaling for Reliability Analysis

June 29, 2016

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…

By Design With Calibre
5 MIN READ
Collaborative SoC Verification

Collaborative SoC Verification

April 11, 2016

By Matthew Hogan, Mentor Graphics The increasing use of SoC designs turns efficient IC design and validation into a team…

By Design With Calibre
4 MIN READ
Automated Power Model Verification for Analog IPs

Automated Power Model Verification for Analog IPs

February 23, 2016

By Sierene Aymen and Hartmut Marquardt, Mentor Graphics Eliminating manual work during power intent verification of analog IPs reduces susceptibility…

By Design With Calibre
4 MIN READ
An Automated Solution for Voltage-Aware DRC

An Automated Solution for Voltage-Aware DRC

February 2, 2016

By Dina Medhat, Mentor Graphics Automated voltage propagation with Calibre PERC makes it easier to comply with voltage-aware DRC spacing…

By Design With Calibre
4 MIN READ
Electromigration and IC Reliability Risk

Electromigration and IC Reliability Risk

January 19, 2016

By Dina Medhat, Mentor Graphics Gradual damage from electromigration can affect product performance and reduce product lifetimes. Reliability analysis ensures…

By Design With Calibre
5 MIN READ
LEF/DEF IO Ring Check Automation

LEF/DEF IO Ring Check Automation

December 15, 2015

By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings…  

By Design With Calibre
5 MIN READ
Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

November 3, 2015

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks on multiple-power-domain and mixed-signal designs…

By Design With Calibre
4 MIN READ
Electrical Overstress Detection and Debugging

Electrical Overstress Detection and Debugging

September 29, 2015

By Dina Medhat, Mentor Graphics Automated voltage propagation provides an accurate way to detect and correct those hard-to-find EOS conditions…

By Design With Calibre
5 MIN READ