PERC

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Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

February 28, 2022

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…

By Design With Calibre
< 1 MIN READ

Stronger together! Context-aware SPICE simulation combines the strengths of static and dynamic verification for faster, more precise full-chip ESD verification

January 31, 2022

By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…

By Design With Calibre
2 MIN READ

Cloud Computing Makes Overnight TAT Attainable

October 11, 2021

By Matthew Hogan and Derong Yan As we all know, during the final sign-off verifications of full chip system-on-chip (SoC)…

By Design With Calibre
3 MIN READ

Caution! Avoid detours when improving resistance on ESD paths

August 19, 2021

By Derong Yan As overall transistor dimensions shrink, integrated circuit (IC) chip designs become more sensitive to the damage caused…

By Design With Calibre
2 MIN READ

2.5/3D IC designers! Don’t get hung up on latch-up!

July 27, 2021

By Dina Medhat Latch-up is modeled as a short circuit (low-impedance path) that occurs in an integrated circuit (IC). It…

By Design With Calibre
2 MIN READ

Don’t hit a roadblock in automotive electronics reliability verification!

July 20, 2021

The recent surge in used car prices may have you wondering what is driving this upswing, and just how much…

By Design With Calibre
2 MIN READ

Do you need an automated ESD verification methodology for 2.5D/3D ICs? If so, read on…

July 8, 2021

By Dina Medhat Electrostatic discharge (ESD) events cause severe damage to unprotected integrated circuits (ICs). You already know that, of…

By Design With Calibre
2 MIN READ

Turn IC verification challenge from a hard slog into a walk in the park by using static checks

May 19, 2021

By Neel Natekar As integrated circuits (ICs) grow in complexity, they create new challenges for IC verification flows and electronic…

By Design With Calibre
2 MIN READ

Give me my space! Why high voltage and multiple power domain designs need automated context-aware spacing checks

April 20, 2021

By Sherif Hany and Abdellah Bakhali Regardless of which technology node they’re using, design houses that create high-voltage and multiple…

By Design With Calibre
2 MIN READ