By Li Li
Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point (P2P) resistance calculations are used in many applications during physical and circuit verification for fast, accurate checks of P2P resistance and CD levels. For example, engineers can use Calibre PERC P2P and CD checking during electrostatic discharge (ESD) verification to determine whether an ESD discharge path is sufficiently robust and efficient. Many foundries provide Calibre PERC rule decks to enable checking of P2P and CD on ESD paths, so it’s highly likely these checks are already available to you. However, most engineers are accustomed to using device-based or cell-based P2P and CD checks, which require time-consuming device and net definitions.
There are many occasions, though, when designers just want to run a quick layout check. For instance, before running full-chip verification, engineers often want to calculate P2P between any two coordinate points of a net in the layout. When an intellectual property (IP) cell is placed in a chip, design teams usually want to check to ensure the IP has robust connections to power, ground, and other signal nets before running specific ESD checks on the full-chip layout. Sometimes a group of nets must be checked to ensure they are the same length from one cell to another. In all of these cases, coordinate-based checks provide a faster and simpler method of running P2P and CD checks, without the need to define complex devices/cells or nets.
Want to learn more about using coordinate-based P2P/CD checks? Check out our technical paper, Enhance IC reliability design verification with coordinate-based P2P and CD checking, for all the details on how you can shave time from your verification flows while still ensuring Calibre confidence in the results!