How to get to Win-Win-Win in conflict management

By Shelly Stalnaker & Calibre Design staff Anyone who’s been through conflict management training understands the three basic scenarios. There’s…

DAC in December?? A Review of Calibre Design Solutions at DAC 2021

Did it feel a bit weird to be submitting research papers for DAC 2022 while packing to go to DAC…

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…

Stronger together! Context-aware SPICE simulation combines the strengths of static and dynamic verification for faster, more precise full-chip ESD verification

By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…

Turn IC verification challenge from a hard slog into a walk in the park by using static checks

By Neel Natekar As integrated circuits (ICs) grow in complexity, they create new challenges for IC verification flows and electronic…

Early circuit verification can get you to tapeout faster…here’s how

For the last few years, it’s been hard to see design teams struggling to meet tapeout schedules caused by increasing…

2021: Time to simplify your life (or at least your workload)?

Everyone makes resolutions for a better life at the start of a new year – why not resolve to make…

A touchy subject: RF IC layout verification

By Neel Natekar – Mentor, A Siemens Business Radio frequency (RF) circuitry is an essential component of many of the…

A new path for analog design constraints verification

A new path for analog design constraints verification

By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for reliability and performance.