Cracking the code: ensuring reliability and performance in IC design with EM/IR analysis

By Karen Chow and Joel Mercier Integrated circuits (ICs) are everywhere, powering everything from washing machines and TVs to medical…

Balancing performance vs. debuggability in LVS circuit verification

By Wael ElManhawy Circuit verification engineers face ever more challenges as semiconductor technology evolves towards smaller process nodes and integrated…

How to verify well layer connectivity with soft checks

By Terry Meeks In the landscape of modern IC chip verification, ensuring the connectivity from diffusion layers to well regions…

The secret to Calibre software quality – AnaCov, our in-house code coverage analysis tool

By Mustafa Naeem, Ahmed Tahoon, Omar Ragi, and Reem El-Adawi In the realm of software testing, accurately tracking and analyzing…

Unraveling the 3DIC shift left strategy: Navigating the world of multi-dimensional ICs

By John Ferguson IC design’s evolution continues to push the boundaries of Moore’s law to new heights. One of the…

Mastering parasitic extraction at the 3 nm process node

By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen…

Why PID issues matter to IC chip designers, and how to combat them

By Derong Yan Integrated circuit (IC) chip designers are constantly striving to meet ever-increasing standards of reliability and performance in…

ERC softchk features

Streamlining IC design verification with Calibre nmLVS Recon

By Kesmat Shahin As integrated circuits (ICs) become more complex, meeting tapeout schedules has become increasingly challenging. Statistics from industry…

Transistor-level EMIR analysis from custom design tools? It’s all about flexibility!

By Roger Kang How do you run transistor-level electromigration and voltage drop (EMIR) analysis—command line or an interactive invocation GUI?…