Unraveling the 3DIC shift left strategy: Navigating the world of multi-dimensional ICs

By John Ferguson IC design’s evolution continues to push the boundaries of Moore’s law to new heights. One of the…

Mastering parasitic extraction at the 3 nm process node

By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen…

Why PID issues matter to IC chip designers, and how to combat them

By Derong Yan Integrated circuit (IC) chip designers are constantly striving to meet ever-increasing standards of reliability and performance in…

ERC softchk features

StreamliningIC design verification with Calibre® nmLVS Recon™

By Kesmat Shahin As integrated circuits (ICs) become more complex, meeting tapeout schedules has become increasingly challenging. Statistics from industry…

Transistor-level EMIR analysis from custom design tools? It’s all about flexibility!

By Roger Kang How do you run transistor-level electromigration and voltage drop (EMIR) analysis—command line or an interactive invocation GUI?…

Optimize metal fill insertion while protecting critical nets and devices…automatically!

By Dina Medhat Context-aware physical verification (PV) is a relatively new addition to traditional PV flows, but it has quickly…

What’s all the fuss about shift left?

By Michael White and David Abercrombie In recent months, it seems as though everyone’s been talking about shift left as…

How can I run reliability checks early in the design cycle?

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff…

ERC softchk features

The secret superpower of early design verification

By Kesmat Shahin How many times, as you traversed across design stages and ran countless iterations, have you wished that…