Turn IC verification challenge from a hard slog into a walk in the park by using static checks

By Neel Natekar As integrated circuits (ICs) grow in complexity, they create new challenges for…

Early circuit verification can get you to tapeout faster…here’s how

For the last few years, it’s been hard to see design teams struggling to meet…

2021: Time to simplify your life (or at least your workload)?

Everyone makes resolutions for a better life at the start of a new year –…

How to get to Win-Win-Win in conflict management

By Dennis Joseph – Mentor, A Siemens Business Anyone who’s been through conflict management training…

A touchy subject: RF IC layout verification

By Neel Natekar – Mentor, A Siemens Business Radio frequency (RF) circuitry is an essential…

A new path for analog design constraints verification

By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for…

Automated Power Model Verification for Analog IPs

By Sierene Aymen and Hartmut Marquardt, Mentor Graphics Eliminating manual work during power intent verification…

You’re Not Alone

By Srinivas Velivala, Mentor Graphics Calibre How-To videos replace your roadblocks with fast solutions for…

My Design’s Interconnect Has Enough Wire Width to Withstand ESD… Doesn’t It?

By Frank Feng, Mentor Graphics Electrostatic discharge can destroy a circuit, but designing adequate protection…