circuit verification

Filter by:

How to get to Win-Win-Win in conflict management

May 2, 2022

By Shelly Stalnaker & Calibre Design staff Anyone who’s been through conflict management training understands the three basic scenarios. There’s…

By Design With Calibre
2 MIN READ

DAC in December?? A Review of Calibre Design Solutions at DAC 2021

March 3, 2022

Did it feel a bit weird to be submitting research papers for DAC 2022 while packing to go to DAC…

By Design With Calibre
4 MIN READ

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

February 28, 2022

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…

By Design With Calibre
< 1 MIN READ

Stronger together! Context-aware SPICE simulation combines the strengths of static and dynamic verification for faster, more precise full-chip ESD verification

January 31, 2022

By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…

By Design With Calibre
2 MIN READ

Turn IC verification challenge from a hard slog into a walk in the park by using static checks

May 19, 2021

By Neel Natekar As integrated circuits (ICs) grow in complexity, they create new challenges for IC verification flows and electronic…

By Design With Calibre
2 MIN READ

Early circuit verification can get you to tapeout faster…here’s how

February 4, 2021

For the last few years, it’s been hard to see design teams struggling to meet tapeout schedules caused by increasing…

By Design With Calibre
2 MIN READ

2021: Time to simplify your life (or at least your workload)?

January 14, 2021

Everyone makes resolutions for a better life at the start of a new year – why not resolve to make…

By Design With Calibre
< 1 MIN READ
A new path for analog design constraints verification

A new path for analog design constraints verification

December 12, 2016

By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for reliability and performance.

By Design With Calibre
5 MIN READ
Automated Power Model Verification for Analog IPs

Automated Power Model Verification for Analog IPs

February 23, 2016

By Sierene Aymen and Hartmut Marquardt, Mentor Graphics Eliminating manual work during power intent verification of analog IPs reduces susceptibility…

By Design With Calibre
4 MIN READ