How can I run reliability checks early in the design cycle?

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff…

ERC softchk features

The secret superpower of early design verification

By Kesmat Shahin How many times, as you traversed across design stages and ran countless iterations, have you wished that…

Struggling to verify the reliability of your multiple-power-domain designs?

By Hossam Sarhan With the growing complexity of system-on-chip designs and technology scaling, multiple power domains are needed to optimize…

Efinix Titanium FPGAs depend on mPower power integrity analysis

By John Wagnon Efinix’s high-performance Titanium FPGAs are custom-tailored for the computing demands of mainstream applications, targeting markets from intelligent…

Google, AMD, and Siemens EDA walk into a cloud…

By Michael White At DAC this past July, I had the opportunity to sit down with Phil Steinke from AMD…

Can you spot the difference?

By James Paris We’ve all played those “Spot the Difference” games where you look at two similar images and try…

Outta my way – electrons coming through!

By Joel Mercier and Karen Chow Ever been in a hurry to get to a meeting, but there were a…

A touchy subject: RF IC layout verification

By Neel Natekar Radio frequency (RF) circuitry is an essential component of many of the critical applications we now rely…

How to get to Win-Win-Win in conflict management

By Shelly Stalnaker & Calibre Design staff Anyone who’s been through conflict management training understands the three basic scenarios. There’s…