Save yourself the time—here’s a way for you to view native block instances from a full-chip context

By Ritu Walia Imagine this: You primarily work on the design of a sub-block of an application-specific layout design, or…

First out of the (3DIC) box: How Siemens EDA is using the TSMC 3Dblox standard to change 3DIC verification

By John Ferguson In recognition of the growing need for a more holistic approach to three-dimensional integrated circuit (3DIC) design,…

Fast, efficient, productive? Your early-stage IC design physical verification can be all that…

By John Ferguson and Nermeen Hossam With each new process node comes more complex requirements needed to ensure working silicon. …

Google, AMD, and Siemens EDA walk into a cloud…

By Michael White At DAC this past July, I had the opportunity to sit down with Phil Steinke from AMD…

Can you spot the difference?

By James Paris We’ve all played those “Spot the Difference” games where you look at two similar images and try…

Improve your layout load time without capital investment?

By Roger Kang How many times has this happened to you—you waited for an hour to complete the loading of…

Optimizing design implementation with Calibre LEF/DEF technology

By James Paris and Armen Asatryan Ever hear the saying “When all you have is a hammer, everything looks like…

Innovations in physical verification tools and technologies keep the IC industry moving forward

By John Ferguson A few years ago, I was invited to present a paper discussing the advances in physical verification…

Accelerating IC design time to market with Calibre in the cloud

By Michael White When you’re flying, it’s fun to look out the window and see clouds from “the other side.”…