Case Studies in P&R Double Patterning Debug: Part Two

David Abercrombie continues his expert advice to P&R and chip finishing engineers on understanding and…

Case Studies in Double-Patterning Debug: Part One

By David Abercrombie, Mentor Graphics Multi-patterning errors in P&R layouts can be intricate, and their…

IoT, Cost-per-Transistor Extend Lifetimes of Established Technology Nodes

By Michael White, Mentor Graphics Much of the Internet of Things (IoT) functionality we crave…

How to Use Pattern Matching to Improve Automatic Waiver Management

By John Ferguson and Jonathan Muirhead, Mentor Graphics Ensuring a known level of quality…

Accurate Lithography Simulation for Silicon Photonics

By Joe Kwan, Mentor Graphics Precise curved geometries are vital to making silicon photonics technology…

Sign-off lithography simulation and multi-patterning must play well together

By Joe Kwan, Mentor Graphics At 20 nm and below, designers must ensure their lithography…

A Look Behind the Mask of Multi-Patterning

By Michael White, Mentor Graphics An overview to the mystery of Multi-Patterning…

Self-Aligned Double Patterning, Part One

By David Abercrombie, Mentor Graphics A walk-through of the SADP process for success.    …