More Than Moore: Finally Crossing the Chasm?

By Michael White, Mentor Graphics Will fan-out wafer-level packaging be the impetus that pushes 3D-IC…

Resetting Expectations on Multi-Patterning Decomposition and Checking Part 2

By David Abercrombie, Mentor Graphics Triple and quadruple patterning can baffle even the most experienced…

Resetting Expectations on Multi-Patterning Decomposition and Checking

By David Abercrombie, Mentor Graphics Some common misconceptions about multi-patterning processes and just how they…

Design Rule Checking for Silicon Photonics

By Ruping Cao, Mentor Graphics Verifying silicon photonics designs requires new techniques, like equation-based DRC…

Reported Death of Moore’s Law Premature?

By Michael White, Mentor Graphics Is Moore’s Law dying? A look at the latest process…

Case Studies in P&R Double Patterning Debug: Part Two

David Abercrombie continues his expert advice to P&R and chip finishing engineers on understanding and…

Case Studies in Double-Patterning Debug: Part One

By David Abercrombie, Mentor Graphics Multi-patterning errors in P&R layouts can be intricate, and their…

IoT, Cost-per-Transistor Extend Lifetimes of Established Technology Nodes

By Michael White, Mentor Graphics Much of the Internet of Things (IoT) functionality we crave…

How to Use Pattern Matching to Improve Automatic Waiver Management

By John Ferguson and Jonathan Muirhead, Mentor Graphics Ensuring a known level of quality…