By Calibre Design Staff
Prior to the availability of extreme ultraviolet (EUV) lithography, multi-patterning provided the only workable yield solution at 20 nm and below. Now, even after the integration of EUV lithography into production processes, it turns out multi-patterning is still required to achieve yield for some processes. But the multi-patterning processes themselves have been changing all the while as well, regardless of which lithography technology the foundry is using. At the most advanced nodes, self-aligned multi-patterning (SAMP) has emerged as a way to overcome the alignment issues inherent in the original multi-patterning techniques.
But just what is SAMP? And what do you need to know about it? Siemens EDA teamed up with IMEC to produce a series of papers explaining the SAMP processes to help foundry engineers, integrated circuit (IC) designers, and verification engineers better understand this somewhat abstruse technology. Think of it this way—if traditional multi-patterning techniques are a complex game of chess, SAMP techniques more closely resemble 4-D chess, in which pieces can be moved in multiple dimensions over time. The ability to foresee the end result requires the proficiency and experience to understand how each move in the process contributes to the desired result.
The first two IMEC/Siemens EDA papers start with the basics—introducing and explaining the different SAMP processes, comparing their advantages and disadvantages, and explaining how engineers can make the best and appropriate choices for their advanced node designs. In the second two papers, we get down to the details and explain the decomposition requirements and techniques for generating the masks used in the SAMP processes, along with guidance on how to avoid or resolve the errors that might occur during their use. All four papers provide detailed explanations and illustrations to help engineers in both foundries and design companies understand the key requirements and inner workings of the SAMP processes, to enable both optimal process selection and the effective implementation of decomposition and checking solutions that can help optimize layouts and mitigate issues.
If you want a SAMPle of the details, all four papers are available for download here: