Smoothing the path to manufacturing success begins with CMP simulation and fill optimization

By Ruben Ghulghazaryan, Davit Piliposyan, Zhengfang Liu, Chunshan Du, Jeff Wilson, Qijian Wan, Xinyi Hu, Zhixi Chen Chemical-mechanical polishing (CMP)…

How to get to Win-Win-Win in conflict management

By Shelly Stalnaker & Calibre Design staff Anyone who’s been through conflict management training understands the three basic scenarios. There’s…

Innovations in physical verification tools and technologies keep the IC industry moving forward

By John Ferguson A few years ago, I was invited to present a paper discussing the advances in physical verification…

Using machine learning to improve DFM: a case study

By Ruben Ghulghazaryan, Davit Piliposyan, Misak Shoyan Several years ago, the American University of Armenia (AUA) and Siemens EDA began…

The path of least resistance…leads to more reliable designs

By Derong Yan Meeting tapeout schedules and performance requirements are equally critical conditions for IC design success. Now engineers can…

Extracting parasitics from MIM/MOM capacitors doesn’t have to hurt!

By Claudia Relyea and Sandeep Koranne  Analog/RF designers need both the speed of rule-based PEX, as well as the capacity…

Accelerating IC design time to market with Calibre in the cloud

By Michael White When you’re flying, it’s fun to look out the window and see clouds from “the other side.”…

Ease on down the road…why “ease of use” is the next big thing in EDA, and how we get there

Ease of use is an important issue when enhancing product functionality and introducing new technology. Calibre Design Systems considers ease…

DRC voltage text annotations: Manually placed texts can be wrong!

By Abdellah Bakhali System-on-chip (SoC) designs often use multiple intellectual property (IP) blocks from multiple IP providers. Each IP provider…