Shift left for more efficient block design and chip integration

Block/chip integration is a lot more complicated than it gets credit for. On the face of it, chip integration just…

Speeding up early design rule checking with Calibre nmDRC Recon

By John Ferguson and Nermeen Hossam Chip designers are very aware of how time-consuming early design rule checking (DRC) can…

Automated analysis-based layout enhancements reduce power grid voltage drops during place & route: A case study with Google

By Jeff Wilson Power isn’t just a small factor in the IC design arena—it’s a cornerstone. Design teams work to…

Accelerate IP design cycles and reduce costs with Calibre design stage verification

By Terry Meeks In the fast-paced world of semiconductor design, time is a critical asset. One way IC designers save…

Balancing performance vs. debuggability in LVS circuit verification

By Wael ElManhawy Circuit verification engineers face ever more challenges as semiconductor technology evolves towards smaller process nodes and integrated…

A new physical verification reporting solution smooths the on-time tapeout effort

By Richard Yan In the intricate world of system-on-chip (SoC) development, Physical Verification (PV) reports serve as vital checkpoints throughout…

How to verify well layer connectivity with soft checks

By Terry Meeks In the landscape of modern IC chip verification, ensuring the connectivity from diffusion layers to well regions…

AI/ML rules at the 2024 SPIE Advanced Lithography + Patterning symposium

The SPIE Advanced Lithography + Pattering symposiums were held from 25-29 February this year with enthusiastic and sizable attendance. The…

Unlocking the future with a digital twin for semiconductor manufacturing

By Srividya Jayaram In semiconductor manufacturing, staying ahead means embracing smarter processes. The rise in demand and the need to…