Stress less, innovate more: ensuring 3D IC reliability with Siemens Calibre 3DStress

The march toward 3D ICs and advanced packaging brings unrivaled performance and integration opportunities—but it also raises new reliability challenges…

Calibre Vision AI: a new era of fast, scalable chip-level DRC debug

By James Paris As chip designs grow more complex and SoCs reach new heights in size and integration, the challenges…

Enhancing EUV lithography resolution at high numerical aperture

By Ethan Maguire As the semiconductor industry continues to push the boundaries of feature size and density, the need for…

Calibre xACT takes a hybrid approach to parasitic extraction

By Mark Tawfik Parasitic extraction plays a pivotal role in the design and optimization of integrated circuits (ICs). Extraction involves…

Smart strategies for metal fill extraction

By Shehab Ashraf As semiconductor technology continues to scale, the impact of parasitic effects from metal fill structures has become…

Solving inter-domain leakage challenges: Enhancing IC design with Insight Analyzer

By Charlie Olson Design reliability remains a top priority for engineers in the world of semiconductor technology. One critical challenge…

Smarter DRC for complex designs: Accelerating verification with Calibre nmDRC Recon

By John Ferguson The challenge: Traditional DRC can’t keep up… Increasing complexity and automation in IC design have made traditional…

Screenshot of the Calibre Interactive GUI showing multiple job submissions.

Easily manage multiple verification jobs with Calibre

Calibre Multiple Job Submission GUI helps you optimize your IC design verification As the complexity of integrated circuits (ICs) continues…

Siemens shines at the 2025 SPIE Advanced Lithography + Patterning symposium

The SPIE Advanced Lithography + Pattering symposiums were held 23-27 February this year with the usual enthusiastic and sizable attendance…