By Hossam Sarhan and Alexandre Arriordaz
With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification to find and correct errors is no longer practical for integrated circuit (IC) design teams. To achieve tapeouts on schedule, designers must now apply reliability verification checks throughout the design flow, from intellectual property (IP) level to full-chip level, to ensure they meet design schedules while confirming design reliability.
But how can designers implement early-stage reliability verification easily and effectively, with assurances that the corrections they apply will pass signoff verification? We can help with that! The Calibre® PERC™ reliability platform packaged checks flow provides pre-coded checks that cover critical design reliability issues, including design topology checks, analog layout reliability verification, and electrostatic discharge (ESD) topological, point to point (P2P) and current density (CD) checks.
These packaged checks are presented in a user-friendly framework that includes a powerful, easy-to-use graphical user interface (GUI) to enable designers to quickly and accurately select and configure checks from the packaged check library. The Calibre PERC packaged checks GUI also supports a full integration with the Calibre Interactive and Calibre RVE results viewer interfaces, providing designers with a seamless experience from selecting, configuring, and running reliability checks to reviewing results with cross-reference highlighting.
Calibre shift-left solutions are designed to provide maximum value to design companies by enabling them to perform early-stage verification. Eliminating critical reliability errors early in the design flow can minimize complex, time-consuming verification iterations later on, enabling design teams to meet tight tapeout schedules and/or implement additional design optimization to improve final design quality and reliability.
Want to learn more about these pre-coded reliability checks, and see how you could be using the Calibre PERC packaged checks GUI to more quickly verify and optimize your designs? Download our technical paper, Pre-layout/post-layout circuit reliability verification…Do it early, do it often, and give it a read!