How to verify well layer connectivity with soft checks

By Terry Meeks In the landscape of modern IC chip verification, ensuring the connectivity from diffusion layers to well regions…

Unlocking the future with a digital twin for semiconductor manufacturing

By Srividya Jayaram In semiconductor manufacturing, staying ahead means embracing smarter processes. The rise in demand and the need to…

Using a shift left strategy to address block/chip design challenges during design-stage verification

By David Abercrombie For IC designers, striking the right balance between tight deadlines and limited resources is a constant challenge….

The secret to Calibre software quality – AnaCov, our in-house code coverage analysis tool

By Mustafa Naeem, Ahmed Tahoon, Omar Ragi, and Reem El-Adawi In the realm of software testing, accurately tracking and analyzing…

Unraveling the 3DIC shift left strategy: Navigating the world of multi-dimensional ICs

By John Ferguson IC design’s evolution continues to push the boundaries of Moore’s law to new heights. One of the…

Mastering parasitic extraction at the 3 nm process node

By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen…

Shifting left with Calibre solutions: Enhancing IP design flow efficiency and design quality

By Terry Meeks Designing integrated circuits (ICs) is a multifaceted task that requires the integration of various components, including intellectual…

ERC softchk features

StreamliningIC design verification with Calibre® nmLVS Recon™

By Kesmat Shahin As integrated circuits (ICs) become more complex, meeting tapeout schedules has become increasingly challenging. Statistics from industry…

3DICs and the multi-physics challenge

By John Ferguson Design teams have known since, well, pretty much forever that mechanical stresses and temperature changes can affect…