What is critical area analysis and why should I care?

By Simon Favre What makes money in the semiconductor industry? A killer IC design? Something…

Automated ESD protection verification for 2.5-3D ICs is now a reality

Got the mid-winter blahs? The post-New Year letdown? Looking for something to rev you up?…

SAFE at home! Attending the Samsung SAFE forum in 2020

By Shelly Stalnaker – Mentor, A Siemens Business Samsung is going virtual with their 2020…

ECO Fill Can Rescue Your SoC Tapeout Schedule

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and…

Will EUV Kill Multi-Patterning?

By David Abercrombie, Mentor Graphics Many people think EUV lithography means the end of multi-patterning….

Using Automated Pattern Matching For SRAM Physical Verification

By Elven Huang, Mentor Graphics Accurate SRAM IP verification can be tricky, but automated pattern…

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs….

Are You (Really) Ready for Your Next Node?

By Michael White, Mentor Graphics Skipping nodes is gaining popularity, but it can bring some…

A Pattern of Success: Calibre Pattern Matching

Calibre Pattern Matching enables innovative DRC and other applications across all process nodes and designs….