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The virtuous cycle of silicon: How Siemens is accelerating the era of Physical AI with NVIDIA cuLitho

October 14, 2026

GPU-accelerated computational lithography with Siemens Calibre and NVIDIA cuLitho By Dr. Jim Shiely, Chief of Staff for Calibre Semiconductor R&D,…

By Calibre IC Design & Manufacturing
4 MIN READ
Top-level schematic of a CMOS Low Dropout voltage regulator. An error amplifier (OA1) drives the gate of a PMOS pass transistor. The critical connection between the amplifier output and the transistor gate is labeled as the "VICTIM" net. The circuit also shows feedback resistors and an output capacitor.

Eliminating the silent killer of analog reliability: A structural approach to floating nets

October 12, 2026

By Bhanu Pandey, Product Engineer, Calibre Design Solutions A successful first silicon run starts with getting the design details right….

By Bhanu Pandey
5 MIN READ

DRC at scale: How Calibre Vision AI turns billions of errors into actionable insights 

August 5, 2026

Accelerate DRC closure for advanced node SoCs with Calibre Vision AI. Real-time, AI-guided analysis shortens debug cycles and enables efficient team collaboration for faster, predictable physical verification.

By Calibre IC Design & Manufacturing
7 MIN READ

Securing your silicon: Why automated IP integrity is non-negotiable in modern SoC design

December 2, 2025

Ensure IP integrity in your SoC designs. Discover how Calibre IP Checker detects hidden IP modifications, prevents costly re-spins and accelerates tape-out.

By Calibre IC Design & Manufacturing
5 MIN READ

Bridging the gap: Unlock seamless collaboration in IC design with Calibre Connectivity Interface

November 5, 2025

Calibre Connectivity Interface (CCI) seamlessly connects EDA tools for advanced IC design verification. It transforms LVS into a powerful data source, enabling critical analyses like parasitic extraction & power integrity.

By Calibre IC Design & Manufacturing
5 MIN READ

Boost simulation results with powerful selective net extraction with Calibre xACT

October 1, 2025

By Karen Chow In advanced integrated circuit (IC) design, post-layout parasitic extraction is crucial for accurate performance analysis and optimization….

By Calibre IC Design & Manufacturing
9 MIN READ

Safeguarding IC reliability: Calibre PERC’s latch-up guard ring check

September 23, 2025

Ensure robust latch-up protection in your ICs with Calibre PERC’s comprehensive ESDA verification checks. Identify and resolve issues early, improve reliability, and accelerate time-to-market.

By Calibre IC Design & Manufacturing
4 MIN READ

Enhancing IC Verification: Smarter solutions for faster, more reliable designs

September 2, 2025

By Jonathan Muirhead Modern chip layouts are more intricate than ever, incorporating a mix of custom and third-party intellectual property…

By Calibre IC Design & Manufacturing
4 MIN READ

Revolutionizing 3D IC design with integrated multiphysics verification

August 12, 2025

By Yoyo Li The semiconductor landscape is always evolving—sometimes quietly, sometimes at breakneck pace. Today, as integrated circuit designs progress…

By Calibre IC Design & Manufacturing
5 MIN READ