Ease on down the road…why “ease of use” is the next big thing in EDA, and how we get there

Ease of use is an important issue when enhancing product functionality and introducing new technology. Calibre Design Systems considers ease…

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…

Want to know what went on at the TSMC OIP Forum this year? Here’s the inside scoop…

TSMC customers and partners always look forward to the annual TSMC Open Innovation Platform® (OIP) Forums. Here, they get the…

Fix first, finish faster!

By James Paris A few years ago, I came across some plans to build a simple bookshelf that would fit…

What is critical area analysis and why should I care?

By Simon Favre What makes money in the semiconductor industry? A killer IC design? Something so innovative that it blows…

Automated ESD protection verification for 2.5-3D ICs is now a reality

Got the mid-winter blahs? The post-New Year letdown? Looking for something to rev you up? How about an automated method…

SAFE at home! Attending the Samsung SAFE forum in 2020

By Shelly Stalnaker – Mentor, A Siemens Business Samsung is going virtual with their 2020 SAFE forum, and Mentor, a…

ECO Fill Can Rescue Your SoC Tapeout Schedule

ECO Fill Can Rescue Your SoC Tapeout Schedule

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and re-verify late-stage changes quickly, while…

Will EUV Kill Multi-Patterning?

Will EUV Kill Multi-Patterning?

By David Abercrombie, Mentor Graphics Many people think EUV lithography means the end of multi-patterning. Do you?