Mastering parasitic extraction at the 3 nm process node

By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen…

Shifting left with Calibre solutions: Enhancing IP design flow efficiency and design quality

By Terry Meeks Designing integrated circuits (ICs) is a multifaceted task that requires the integration of various components, including intellectual…

ERC softchk features

Streamlining IC design verification with Calibre nmLVS Recon

By Kesmat Shahin As integrated circuits (ICs) become more complex, meeting tapeout schedules has become increasingly challenging. Statistics from industry…

3DICs and the multi-physics challenge

By John Ferguson Design teams have known since, well, pretty much forever that mechanical stresses and temperature changes can affect…

Elevating user experience with UX maturity models

By Kirolos George and Reem El Adawi In today’s digital landscape, user experience (UX) plays a crucial role in the…

Sanity check: Will automated fill back-annotation help?

By James Paris Hey there, custom integrated circuit (IC) design engineers! If you’re knee-deep in the world of IC design,…

Optimize metal fill insertion while protecting critical nets and devices…automatically!

By Dina Medhat Context-aware physical verification (PV) is a relatively new addition to traditional PV flows, but it has quickly…

Are you a C++ developer or programmer? You may want to read this…

By day, Fedor Pikus is head of the Advanced Projects Team in Siemens Digital Industries Software. His responsibilities include planning…

Introducing Calibre DesignEnhancer design-stage layout optimization!

By Jeff Wilson Introduced in early 2023, the Calibre DesignEnhancer tool is part of a growing suite of shift-left tools…