2021: Time to simplify your life (or at least your workload)?

Everyone makes resolutions for a better life at the start of a new year –…

Verification run configurations stressing you out? Automate them!

By Srinivas Velivala – Mentor, A Siemens Business As all new IC verification engineers learn…

ECO Fill Can Rescue Your SoC Tapeout Schedule

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and…

Will EUV Kill Multi-Patterning?

By David Abercrombie, Mentor Graphics Many people think EUV lithography means the end of multi-patterning….

Using Automated Pattern Matching For SRAM Physical Verification

By Elven Huang, Mentor Graphics Accurate SRAM IP verification can be tricky, but automated pattern…

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs….

Are You (Really) Ready for Your Next Node?

By Michael White, Mentor Graphics Skipping nodes is gaining popularity, but it can bring some…

A Pattern of Success: Calibre Pattern Matching

Calibre Pattern Matching enables innovative DRC and other applications across all process nodes and designs….

A new path for analog design constraints verification

By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for…