ic verification

Interactive symmetry checking for analog/custom ICs: Faster, easier, more accurate

July 6, 2022

By Sara Khalaf While the reliability and performance of multiple types of designs such as analog, MEMs, and image sensors…

By Design With Calibre
2 MIN READ

Innovations in physical verification tools and technologies keep the IC industry moving forward

April 20, 2022

By John Ferguson A few years ago, I was invited to present a paper discussing the advances in physical verification…

By Design With Calibre
2 MIN READ

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

February 28, 2022

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…

By Design With Calibre
< 1 MIN READ

2021: Time to simplify your life (or at least your workload)?

January 14, 2021

Everyone makes resolutions for a better life at the start of a new year – why not resolve to make…

By Design With Calibre
< 1 MIN READ

Verification run configurations stressing you out? Automate them!

November 12, 2020

By Srinivas Velivala – Mentor, A Siemens Business As all new IC verification engineers learn very quickly, there is far…

By Design With Calibre
2 MIN READ
ECO Fill Can Rescue Your SoC Tapeout Schedule

ECO Fill Can Rescue Your SoC Tapeout Schedule

February 27, 2017

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and re-verify late-stage changes quickly, while…

By Design With Calibre
5 MIN READ
Will EUV Kill Multi-Patterning?

Will EUV Kill Multi-Patterning?

January 25, 2017

By David Abercrombie, Mentor Graphics Many people think EUV lithography means the end of multi-patterning. Do you?

By Design With Calibre
8 MIN READ
Using Automated Pattern Matching For SRAM Physical Verification

Using Automated Pattern Matching For SRAM Physical Verification

January 17, 2017

By Elven Huang, Mentor Graphics Accurate SRAM IP verification can be tricky, but automated pattern matching can help.

By Design With Calibre
6 MIN READ
Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

January 16, 2017

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs.

By Design With Calibre
< 1 MIN READ