Balancing performance vs. debuggability in LVS circuit verification

By Wael ElManhawy Circuit verification engineers face ever more challenges as semiconductor technology evolves towards smaller process nodes and integrated…

How to verify well layer connectivity with soft checks

By Terry Meeks In the landscape of modern IC chip verification, ensuring the connectivity from diffusion layers to well regions…

Using a shift left strategy to address block/chip design challenges during design-stage verification

By David Abercrombie For IC designers, striking the right balance between tight deadlines and limited resources is a constant challenge….

The secret to Calibre software quality – AnaCov, our in-house code coverage analysis tool

By Mustafa Naeem, Ahmed Tahoon, Omar Ragi, and Reem El-Adawi In the realm of software testing, accurately tracking and analyzing…

Shifting left with Calibre solutions: Enhancing IP design flow efficiency and design quality

By Terry Meeks Designing integrated circuits (ICs) is a multifaceted task that requires the integration of various components, including intellectual…

Elevating user experience with UX maturity models

By Kirolos George and Reem El Adawi In today’s digital landscape, user experience (UX) plays a crucial role in the…

Sanity check: Will automated fill back-annotation help?

By James Paris Hey there, custom integrated circuit (IC) design engineers! If you’re knee-deep in the world of IC design,…

Streamlining semiconductor verification with the Calibre Interactive interface

By Slava Zhuchenya In the world of semiconductors, creating and verifying IC designs is no cakewalk. It’s a complex dance…

Transistor-level EMIR analysis from custom design tools? It’s all about flexibility!

By Roger Kang How do you run transistor-level electromigration and voltage drop (EMIR) analysis—command line or an interactive invocation GUI?…