Innovations in physical verification tools and technologies keep the IC industry moving forward

By John Ferguson A few years ago, I was invited to present a paper discussing the advances in physical verification…

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…

2021: Time to simplify your life (or at least your workload)?

Everyone makes resolutions for a better life at the start of a new year – why not resolve to make…

Verification run configurations stressing you out? Automate them!

By Srinivas Velivala – Mentor, A Siemens Business As all new IC verification engineers learn very quickly, there is far…

ECO Fill Can Rescue Your SoC Tapeout Schedule

ECO Fill Can Rescue Your SoC Tapeout Schedule

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and re-verify late-stage changes quickly, while…

Will EUV Kill Multi-Patterning?

Will EUV Kill Multi-Patterning?

By David Abercrombie, Mentor Graphics Many people think EUV lithography means the end of multi-patterning. Do you?

Using Automated Pattern Matching For SRAM Physical Verification

Using Automated Pattern Matching For SRAM Physical Verification

By Elven Huang, Mentor Graphics Accurate SRAM IP verification can be tricky, but automated pattern matching can help.

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs.

Are You (Really) Ready for Your Next Node?

Are You (Really) Ready for Your Next Node?

By Michael White, Mentor Graphics Skipping nodes is gaining popularity, but it can bring some unexpected challenges. Are you prepared?