ESD protection

Do you trust the reliability of your 2.5D/3D IC package designs?

March 9, 2022

By Dina Medhat 2.5D/3D ICs have become an innovative solution for many design and integration challenges. Basic physical verification for…

By Design With Calibre
3 MIN READ

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

February 28, 2022

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…

By Design With Calibre
1 MIN READ

In the EDA world, efficiency + ease of use = productivity (and profitability!)

October 21, 2021

By Shelly Stalnaker Electronic design automation (EDA) grew out of the need to make it easier and faster to design…

By Design With Calibre
2 MIN READ

Caution! Avoid detours when improving resistance on ESD paths

August 19, 2021

By Derong Yan As overall transistor dimensions shrink, integrated circuit (IC) chip designs become more sensitive to the damage caused…

By Design With Calibre
2 MIN READ

Do you need an automated ESD verification methodology for 2.5D/3D ICs? If so, read on…

July 8, 2021

By Dina Medhat Electrostatic discharge (ESD) events cause severe damage to unprotected integrated circuits (ICs). You already know that, of…

By Design With Calibre
2 MIN READ

Automated ESD protection verification for 2.5-3D ICs is now a reality

January 28, 2021

Got the mid-winter blahs? The post-New Year letdown? Looking for something to rev you up? How about an automated method…

By Design With Calibre
2 MIN READ

Help! I’m not an ESD expert! Reducing ESD verification complexity

November 4, 2020

By Abdellah Bakhali – Mentor, A Siemens Business If you’re not an ESD expert (and let’s face it, most of…

By Design With Calibre
3 MIN READ
Transistor level ESD verification in large SoC designs

Transistor level ESD verification in large SoC designs

October 31, 2016

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help

By Design With Calibre
4 MIN READ
LEF/DEF IO Ring Check Automation

LEF/DEF IO Ring Check Automation

December 15, 2015

By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings…  

By Design With Calibre
5 MIN READ