In the EDA world, efficiency + ease of use = productivity (and profitability!)

By Shelly Stalnaker Electronic design automation (EDA) grew out of the need to make it…

Caution! Avoid detours when improving resistance on ESD paths

By Derong Yan As overall transistor dimensions shrink, integrated circuit (IC) chip designs become more…

Do you need an automated ESD verification methodology for 2.5D/3D ICs? If so, read on…

By Dina Medhat Electrostatic discharge (ESD) events cause severe damage to unprotected integrated circuits (ICs)….

Automated ESD protection verification for 2.5-3D ICs is now a reality

Got the mid-winter blahs? The post-New Year letdown? Looking for something to rev you up?…

Help! I’m not an ESD expert! Reducing ESD verification complexity

By Abdellah Bakhali – Mentor, A Siemens Business If you’re not an ESD expert (and…

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation…

LEF/DEF IO Ring Check Automation

By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning…