Calibre IC Design & Manufacturing

From chaos to clarity: Smarter DRC workflows and team productivity with Calibre Vision AI

August 20, 2026

Advanced node DRC demands rapid team coordination and closure. You can transform your entire DRC workflow by turning massive error data into...

By Calibre IC Design & Manufacturing

< 1 MIN READ

DRC at scale: How Calibre Vision AI turns billions of errors into actionable insights

August 5, 2026

Accelerate DRC closure for advanced node SoCs with Calibre Vision AI. Real-time, AI-guided analysis shortens debug cycles and enables efficient team collaboration for faster, predictable physical verification.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Interactive symmetry checking with Calibre RealTime accelerates analog IC design

July 24, 2026

Learn how Calibre RealTime enables interactive symmetry checking in analog IC design with instant validation, zero setup and early detection to compress schedules and reduce costly rework

By Calibre IC Design & Manufacturing

< 1 MIN READ

The Calibre 3D IC solution: Mastering the complexities of advanced 3D IC chip design

May 14, 2026

Optimize 3D IC chip design from concept to sign-off with Calibre 3D IC solutions. Achieve accurate electro-thermo-mechanical co-simulation, prevent costly errors, and accelerate time-to-market.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Tackling compute complexity in ESD verification with Calibre

April 23, 2026

Explore how Calibre PERC and Calibre 3DPERC tackle the escalating compute complexity of ESD verification in advanced IC designs, including 2.5D and 3DIC structures, ensuring robust protection and signoff-quality results

By Calibre IC Design & Manufacturing

< 1 MIN READ

Why a GPU rasterizer matters for computational lithography in both performance and precision at scale

April 13, 2026

This technical analysis explores GPU rasterizer for accelerated mask synthesis. Benchmarks show 290x speedup for Manhattan geometries and 45x for curvilinear shapes with <1% error.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Meeting the challenges of reliability verification for the era of 3D ICs

April 1, 2026

Advanced reliability verification for 2.5D/3D ICs with Innovator3D IC and Calibre 3DPERC. Ensure robust reliability and accelerate sign-off.

By Calibre IC Design & Manufacturing

< 1 MIN READ

From data to domain expertise: How AI, accelerated computing and digital twins are reshaping semiconductor manufacturing

March 20, 2026

Explore the dawn of industrial AI in semiconductor manufacturing. Learn how Siemens EDA is leveraging AI, digital twins, and GPU-accelerated computing to empower engineers, automate workflows, and build smarter factories.

By Calibre IC Design & Manufacturing

< 1 MIN READ

ICYMI: Siemens EDA at 2026 SPIE Advanced Lithography + Patterning

March 9, 2026

Read about Calibre Manufacturing’s highlights from the 2025 SPIE Advanced Lithography Patterning symposium.

By Calibre IC Design & Manufacturing

< 1 MIN READ

The engineering talent pipeline: How Siemens is helping to build tomorrow's workforce

March 4, 2026

Siemens EDA recognizes that the future of manufacturing depends on a robust pipeline of skilled talent. That’s why we have partnered with ChipsHub to be part of a comprehensive workforce development ecosystem

By Calibre IC Design & Manufacturing

< 1 MIN READ

How to use Calibre parasitic extraction tools: a step-by-step guide

February 18, 2026

A step by step guide designed to help users master the Calibre parasitic extraction tools

By Calibre IC Design & Manufacturing

< 1 MIN READ

Siemens acquires Canopus AI: Supercharging semiconductor manufacturing with AI-powered metrology

February 4, 2026

Siemens acquires Canopus AI to advance semiconductor manufacturing with AI-powered metrology and inspection, boosting precision, efficiency, and yield.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre IC Manufacturing in 2025: The year’s biggest news

January 29, 2026

Read about 2025 highlights from Siemens Calibre IC Manufacturing group, including advances in computational metrology, monotonic machine learning, AI, EUV and GPU acceleration

By Calibre IC Design & Manufacturing

< 1 MIN READ

ESD verification in 3D ICs: Navigating unseen risks and new realities

January 21, 2026

Discover best practices for automated 3D IC ESD verification using Calibre 3DPERC. Learn how to address the unique challenges of ESD protection in advanced 3D IC designs and ensure system-level reliability.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre IC Design in 2025: AI, 3D IC advancement and shift-left strategies drive verification excellence

January 12, 2026

Read about 2025 IC Design highlights from Siemens Calibre, including AI-powered verification and debug, 3D IC innovations, and shift-left strategies supporting accelerated tapeouts.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Securing your silicon: Why automated IP integrity is non-negotiable in modern SoC design

December 2, 2025

Ensure IP integrity in your SoC designs. Discover how Calibre IP Checker detects hidden IP modifications, prevents costly re-spins and accelerates tape-out.

By Calibre IC Design & Manufacturing

< 1 MIN READ

6 frequent design rule checking errors every IC designer should know – and how Calibre nmDRC helps you avoid them

November 18, 2025

Learn about some common design rule checking (DRC) violations in integrated circuit layouts—and how Calibre nmDRC helps engineers catch, analyze and resolve them quickly to ensure first-pass silicon success.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Bridging the gap: Unlock seamless collaboration in IC design with Calibre Connectivity Interface

November 5, 2025

Calibre Connectivity Interface (CCI) seamlessly connects EDA tools for advanced IC design verification. It transforms LVS into a powerful data source, enabling critical analyses like parasitic extraction & power integrity.

By Calibre IC Design & Manufacturing

< 1 MIN READ

The IC designers complete guide to design rule checking

October 30, 2025

Design rule checking (DRC) ensures IC layouts meet foundry rules. Learn how modern DRC engines like Calibre deliver scalable, sign-off accuracy at advanced nodes

By Calibre IC Design & Manufacturing

< 1 MIN READ

IC visualization: Supercharge debug of hidden parasitic threats with Calibre

October 27, 2025

By Omar Elabd If you’ve ever watched your simulation pass with flying colors, only to see your silicon fail in...

By Calibre IC Design & Manufacturing

< 1 MIN READ

From translator to powerhouse: Calibre V2LVS second generation redefines LVS verification

October 16, 2025

Explore second-generation Calibre Verilog-to-LVS: up to 4X faster runtimes, 92% less memory use, smarter debugging and robust SoC verification for advanced digital designs

By Calibre IC Design & Manufacturing

< 1 MIN READ

Design rule checking in today’s integrated circuit design environment

October 6, 2025

Explore integrated circuit design rule checking (DRC) in modern integrated circuit design, from increasing complexity to fast-feedback solutions like Calibre nmDRC Recon. Learn use cases, challenges and future trends.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Boost simulation results with powerful selective net extraction with Calibre xACT

October 1, 2025

By Karen Chow In advanced integrated circuit (IC) design, post-layout parasitic extraction is crucial for accurate performance analysis and optimization....

By Calibre IC Design & Manufacturing

< 1 MIN READ

Safeguarding IC reliability: Calibre PERC's latch-up guard ring check

September 23, 2025

Ensure robust latch-up protection in your ICs with Calibre PERC's comprehensive ESDA verification checks. Identify and resolve issues early, improve reliability, and accelerate time-to-market.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Driving 3D IC innovation with Calibre multiphysics

September 18, 2025

Explore how Siemens EDA’s multiphysics workflow helps design teams to overcome the thermal, stress and reliability challenges of 3D ICs. Learn why early, integrated analysis with tools like Calibre 3DSTACK and Innovator3D IC is critical to success in advanced chiplet design.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Siemens-imec collaboration reduces stochastic failures in EUV lithography by orders of magnitude in wafer-level experimental validation

September 11, 2025

Siemens stochastic-aware OPC reduces EUV stochastic failures at wafer level for SRAM and logic, validating predictive modeling with experimental data.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Enhancing IC Verification: Smarter solutions for faster, more reliable designs

September 2, 2025

By Jonathan Muirhead Modern chip layouts are more intricate than ever, incorporating a mix of custom and third-party intellectual property...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Revolutionizing 3D IC design with integrated multiphysics verification

August 12, 2025

By Yoyo Li The semiconductor landscape is always evolving—sometimes quietly, sometimes at breakneck pace. Today, as integrated circuit designs progress...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How to boost reliability with early-stage reliability checks

July 23, 2025

By Chun-hsiang Chang The rapid expansion of AI-powered consumer electronics is pushing IC manufacturing to the sub-2 nm frontier. To...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Navigating 3D IC stress: physical realities and best practices for 3D IC reliability

July 16, 2025

By Shetha Nolke As the semiconductor industry shifts toward heterogeneous 3D ICs, exciting benefits are coming within reach—from smaller footprints...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Ensure power domain compatibility by finding missing level shifters with Insight Analyzer

July 9, 2025

By Bhanu Pandey Level shifters are essential for safe, reliable mixed-signal IC design—especially as designers deploy more power domains than...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Stress less, innovate more: ensuring 3D IC reliability with Siemens Calibre 3DStress

July 2, 2025

The march toward 3D ICs and advanced packaging brings unrivaled performance and integration opportunities—but it also raises new reliability challenges...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre Vision AI: a new era of fast, scalable chip-level DRC debug

June 25, 2025

By James Paris As chip designs grow more complex and SoCs reach new heights in size and integration, the challenges...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Enhancing EUV lithography resolution at high numerical aperture

June 6, 2025

By Ethan Maguire As the semiconductor industry continues to push the boundaries of feature size and density, the need for...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Overcoming noise challenges in analog and RF circuit design with Calibre PERC net shielding

May 20, 2025

By Hossam Sarhan Communication has become the backbone of everything from personal routines to industry, and the demand for analog...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre xACT takes a hybrid approach to parasitic extraction

May 12, 2025

By Mark Tawfik Parasitic extraction plays a pivotal role in the design and optimization of integrated circuits (ICs). Extraction involves...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Smart strategies for metal fill extraction

April 29, 2025

By Shehab Ashraf As semiconductor technology continues to scale, the impact of parasitic effects from metal fill structures has become...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Solving inter-domain leakage challenges: Enhancing IC design with Insight Analyzer

April 10, 2025

By Charlie Olson Design reliability remains a top priority for engineers in the world of semiconductor technology. One critical challenge...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Smarter DRC for complex designs: Accelerating verification with Calibre nmDRC Recon

April 2, 2025

By John Ferguson The challenge: Traditional DRC can’t keep up… Increasing complexity and automation in IC design have made traditional...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Easily manage multiple verification jobs with Calibre

March 19, 2025

Calibre Multiple Job Submission GUI helps you optimize your IC design verification As the complexity of integrated circuits (ICs) continues...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Siemens shines at the 2025 SPIE Advanced Lithography + Patterning symposium

March 13, 2025

The SPIE Advanced Lithography + Pattering symposiums were held 23-27 February this year with the usual enthusiastic and sizable attendance...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Solving IR drop and layout bottlenecks: How Calibre DesignEnhancer streamlines IC design

March 12, 2025

By Jeff Wilson As an IC designer, you know that achieving an optimal layout is about more than just meeting...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Transforming pre-layout IC reliability analysis with Siemens Insight Analyzer

January 22, 2025

By Matthew Hogan As the industry continues to push the boundaries of what’s possible in IC design, the need for...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Unlocking post-tapeout flow scalability and performance with cloud computing

January 8, 2025

By Bassem Riad As process geometries continue to shrink, computational lithography demands increasingly powerful and abundant CPU resources to support...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Siemens EDA and TSMC partner to advance 3D IC Design

December 18, 2024

As the semiconductor industry continues to push the boundaries of innovation, the need for advanced 3D IC design solutions has...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Shift left with Calibre interactive symmetry checking to improve design efficiency

December 10, 2024

By Sara Khalaf Symmetry plays a crucial role in IC design by ensuring balanced device behavior, minimizing mismatch, and improving...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Navigating ESD challenges in 2.5D/3D ICs: A guide to robust automated verification

November 19, 2024

By Dina Medhat Electrostatic discharge (ESD) events cause severe damage to unprotected integrated circuits (ICs). ESD events cause severe damage...

By Calibre IC Design & Manufacturing

< 1 MIN READ

An introduction to advanced verification techniques for IC design symmetry

November 13, 2024

By Jonathan Muirhead Integrated circuit (IC) design, particularly for analog and radio frequency (RF) circuits, involves meticulous attention to detail...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Siemens Calibre 3DThermal wins 2024 WEAA award for innovation in 3D IC thermal analysis

November 12, 2024

Siemens Digital Industries Software’s Calibre® 3DThermal tool was awarded the 2024 AspenCore World Electronics Achievement Award (WEAA) in the EDA/IP/Software...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Dr. Fedor Pikus cultivates engineering talent in Armenia

November 7, 2024

The semiconductor market depends on the work of talented engineers, but the supply of qualified engineers worldwide hasn’t kept pace...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Shift left in IC design: A holistic strategy for faster, smarter verification

October 30, 2024

By Michael White and David Abercrombie As IC design complexity continues to grow, companies are turning to the shift left...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Tom Quan is now officially retired from TSMC

October 22, 2024

For those of us in Semiconductor Ecosystem, watching the TSMC OIP (Open Innovation Platform) evolve from a fledgling foundry event...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Enhanced short isolation process for faster circuit verification

October 21, 2024

By Ritu Walia Repetitive layout vs. schematic (LVS) runs can significantly delay project timelines. A huge number of shorted nets...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Unveiling the future of 3DIC design with Calibre 3DThermal

October 9, 2024

By Lee Wang The semiconductor industry is undergoing a transformative shift from traditional 2D integrated circuit (IC) designs to more...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Navigating the complex world of resistance extraction for curvilinear shapes in IC designs

September 26, 2024

By Nada Tarek As integrated circuit (IC) designs continue to push the boundaries of what’s possible, we’re seeing an explosion...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Optimal ESD protection with Calibre PERC and Solido Simulation Suite

September 17, 2024

By Neel Natekar Integrated circuit (IC) reliability engineers face the dual challenge of ensuring robust electrostatic discharge (ESD) protection without...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Cloud Flight Plans enable cost-effective use of the cloud for peak productivity

September 5, 2024

By Chris Clee You might ask, “What on Earth is a Cloud Flight Plan?” It’s a collection of best practices...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Faster design verification with Calibre nmLVS Recon Compare

August 22, 2024

By Wael ElManhawy Layout versus schematic (LVS) comparison is a fundamental step in integrated circuit (IC) design verification. It ensures...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Cracking the code: ensuring reliability and performance in IC design with EM/IR analysis

August 5, 2024

By Karen Chow and Joel Mercier Integrated circuits (ICs) are everywhere, powering everything from washing machines and TVs to medical...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Shift left for more efficient block design and chip integration

July 26, 2024

Block/chip integration is a lot more complicated than it gets credit for. On the face of it, chip integration just...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Speeding up early design rule checking with Calibre nmDRC Recon

June 5, 2024

By John Ferguson and Nermeen Hossam Chip designers are very aware of how time-consuming early design rule checking (DRC) can...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Automated analysis-based layout enhancements reduce power grid voltage drops during place & route: A case study with Google

May 29, 2024

By Jeff Wilson Power isn’t just a small factor in the IC design arena—it’s a cornerstone. Design teams work to...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Accelerate IP design cycles and reduce costs with Calibre design stage verification

May 6, 2024

By Terry Meeks In the fast-paced world of semiconductor design, time is a critical asset. One way IC designers save...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Balancing performance vs. debuggability in LVS circuit verification

April 23, 2024

By Wael ElManhawy Circuit verification engineers face ever more challenges as semiconductor technology evolves towards smaller process nodes and integrated...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A new physical verification reporting solution smooths the on-time tapeout effort

April 16, 2024

By Richard Yan In the intricate world of system-on-chip (SoC) development, Physical Verification (PV) reports serve as vital checkpoints throughout...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How to verify well layer connectivity with soft checks

April 10, 2024

By Terry Meeks In the landscape of modern IC chip verification, ensuring the connectivity from diffusion layers to well regions...

By Calibre IC Design & Manufacturing

< 1 MIN READ

AI/ML rules at the 2024 SPIE Advanced Lithography + Patterning symposium

April 3, 2024

The SPIE Advanced Lithography + Pattering symposiums were held from 25-29 February this year with enthusiastic and sizable attendance. The...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Unlocking the future with a digital twin for semiconductor manufacturing

March 29, 2024

By Srividya Jayaram In semiconductor manufacturing, staying ahead means embracing smarter processes. The rise in demand and the need to...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Using a shift left strategy to address block/chip design challenges during design-stage verification

March 21, 2024

By David Abercrombie For IC designers, striking the right balance between tight deadlines and limited resources is a constant challenge....

By Calibre IC Design & Manufacturing

< 1 MIN READ

How to get accurate inductance extraction for superconductor ICs

March 15, 2024

By Hossam Sarhan and Dusan Petranovic Supporting the high performance and reliability needed for artificial intelligence (AI), data centers and...

By Calibre IC Design & Manufacturing

< 1 MIN READ

The secret to Calibre software quality – AnaCov, our in-house code coverage analysis tool

March 7, 2024

By Mustafa Naeem, Ahmed Tahoon, Omar Ragi, and Reem El-Adawi In the realm of software testing, accurately tracking and analyzing...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Unraveling the 3DIC shift left strategy: Navigating the world of multi-dimensional ICs

February 22, 2024

By John Ferguson IC design’s evolution continues to push the boundaries of Moore’s law to new heights. One of the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Mastering parasitic extraction at the 3 nm process node

February 13, 2024

By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Why PID issues matter to IC chip designers, and how to combat them

February 8, 2024

By Derong Yan Integrated circuit (IC) chip designers are constantly striving to meet ever-increasing standards of reliability and performance in...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Shifting left with Calibre solutions: Enhancing IP design flow efficiency and design quality

January 31, 2024

By Terry Meeks Designing integrated circuits (ICs) is a multifaceted task that requires the integration of various components, including intellectual...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Revolutionizing software testing: Introducing TCP-Net++

January 24, 2024

By Mohamed Abdelkarim and Reem El Adawi In the dynamic world of software development, balancing speedy delivery with quality assurance...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Streamlining IC design verification with Calibre nmLVS Recon

January 3, 2024

By Kesmat Shahin As integrated circuits (ICs) become more complex, meeting tapeout schedules has become increasingly challenging. Statistics from industry...

By Calibre IC Design & Manufacturing

< 1 MIN READ

3DICs and the multi-physics challenge

December 11, 2023

By John Ferguson Design teams have known since, well, pretty much forever that mechanical stresses and temperature changes can affect...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Elevating user experience with UX maturity models

November 29, 2023

By Kirolos George and Reem El Adawi In today’s digital landscape, user experience (UX) plays a crucial role in the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Inspiring the next generation of EDA engineers

November 17, 2023

As the semiconductor market grows, so does the need for qualified engineers throughout the semiconductor ecosystem. Of course, the supply...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How to extend DTCO for today’s competitive IC landscape

November 8, 2023

By Le Hong As semiconductor components continue to shrink, the challenges associated with design-for-manufacturing (DFM) and design-technology co-optimization (DTCO) increase....

By Calibre IC Design & Manufacturing

< 1 MIN READ

Sanity check: Will automated fill back-annotation help?

October 25, 2023

By James Paris Hey there, custom integrated circuit (IC) design engineers! If you’re knee-deep in the world of IC design,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Streamlining semiconductor verification with the Calibre Interactive interface

October 17, 2023

By Slava Zhuchenya In the world of semiconductors, creating and verifying IC designs is no cakewalk. It’s a complex dance...

By Calibre IC Design & Manufacturing

< 1 MIN READ

IC designers: let's talk about shift left strategies

September 28, 2023

By John Ferguson In the constantly evolving world of electronics, where demands are high for more powerful, efficient, and reliable...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Transistor-level EMIR analysis from custom design tools? It’s all about flexibility!

September 20, 2023

By Roger Kang How do you run transistor-level electromigration and voltage drop (EMIR) analysis—command line or an interactive invocation GUI?...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Save yourself the time—here’s a way for you to view native block instances from a full-chip context

September 14, 2023

By Ritu Walia Imagine this: You primarily work on the design of a sub-block of an application-specific layout design, or...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre PERC checks meet Calibre RVE default views: A match made in debugging heaven?

September 6, 2023

By Neel Natekar As technology node scaling continues, integrated circuit (IC) designers are facing increasing physical verification challenges due, in...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A recap of Calibre at DAC 2023

August 29, 2023

DAC is back! At least was the feeling on the floor, judging by the number of attendees we talked to,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Updating a Calibre DesignEnhancer via insertion kit is fast and easy!

August 21, 2023

By Jimmy Tien The Calibre® DesignEnhancer Via use model provides an automated via insertion process based on foundry design rule...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Optimize metal fill insertion while protecting critical nets and devices...automatically!

August 15, 2023

By Dina Medhat Context-aware physical verification (PV) is a relatively new addition to traditional PV flows, but it has quickly...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Are you a C++ developer or programmer? You may want to read this…

August 10, 2023

By day, Fedor Pikus is head of the Advanced Projects Team in Siemens Digital Industries Software. His responsibilities include planning...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre IC manufacturing research for what comes next

August 3, 2023

By Germain Fenger Director of Product Management RET modeling, Calibre Semiconductor Manufacturing Solutions There is no rest in semiconductor manufacturing....

By Calibre IC Design & Manufacturing

< 1 MIN READ

Introducing Calibre DesignEnhancer design-stage layout optimization!

July 18, 2023

By Jeff Wilson Introduced in early 2023, the Calibre DesignEnhancer tool is part of a growing suite of shift-left tools...

By Calibre IC Design & Manufacturing

< 1 MIN READ

AUA students meet Siemens EDA!

July 11, 2023

By Armen Asatryan On June 14, a group of twelve students from the American University of Armenia (AUA), several faculty...

By Calibre IC Design & Manufacturing

< 1 MIN READ

What’s all the fuss about shift left?

July 6, 2023

By Michael White and David Abercrombie In recent months, it seems as though everyone’s been talking about shift left as...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Cross-platform database validation: Don’t add applications without it!

April 25, 2023

By James Paris The OASIS* database format is a widely used industry standard in electronic design automation (EDA) software for...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Why take chances with your PV job setups when a winning alternative is available?

April 18, 2023

By Richard Yan Are you interested in optimizing your integrated circuit (IC) physical verification (PV) flows? How does automating the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How can I run reliability checks early in the design cycle?

April 11, 2023

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Siemens EDA celebrates 20 years of collaboration with imec

March 28, 2023

By Germain Fenger, Director of Product Management RET modelingCalibre Semiconductor Manufacturing solutions This year marks the 20th anniversary of the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

First out of the (3DIC) box: How Siemens EDA is using the TSMC 3Dblox standard to change 3DIC verification

March 27, 2023

By John Ferguson In recognition of the growing need for a more holistic approach to three-dimensional integrated circuit (3DIC) design,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A novel methodology for EM assessment in on-power grids can improve power, time-to-market, and design cost

March 10, 2023

By Valeriy Sukharev, Armen Kteyan, Jun-Ho Choy Achieving an accurate assessment of electromigration (EM)-induced failure is essential to developing a...

By Calibre IC Design & Manufacturing

< 1 MIN READ

The secret superpower of early design verification

March 2, 2023

By Kesmat Shahin How many times, as you traversed across design stages and ran countless iterations, have you wished that...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Help! I’m not an ESD expert! Reducing ESD verification complexity

February 9, 2023

By Abdellah Bakhali If you’re not an electrostatic discharge (ESD) expert (and let’s face it, most of us aren’t), verifying...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Automated common resistance checking…it’s the smart thing to do!

January 30, 2023

By Hossam Sarhan Work smarter, not harder. Isn’t that what everyone is always telling you? Of course, it’s excellent advice,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A software migration that improves productivity? The Calibre Interactive tool has a (new) GUI for that…

January 26, 2023

By Slava Zhuchenya Software migration can be a dreaded endeavor, especially for electronic design automation (EDA) tools that design companies...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Find high resistance faster in P2P violations with interactive P2P analysis

January 16, 2023

By Slava Zhuchenya So your net trace has too much parasitic resistance. Where is it coming from? You ran your...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A new method of scaling and efficiency for the semi-manufacturing flow

January 9, 2023

By Beth Martin Calibre sets sail on Kubernetes While most Calibre semi-manufacturing jobs still run on on-premises compute clusters using...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Abracadabra! Clearing shorts before full-chip implementation

December 20, 2022

By James Paris and Armen Asatryan Automated short checking during implementation lets design teams quickly find and fix these errors...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Fast, efficient, productive? Your early-stage IC design physical verification can be all that…

December 14, 2022

By John Ferguson and Nermeen Hossam With each new process node comes more complex requirements needed to ensure working silicon. ...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Infineon and Siemens collaborate for innovation

December 7, 2022

By Karen Chow When Infineon needed to select a field solver for the development of their next-generation power semiconductor products,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

mPower power integrity analysis solution recognized for innovation and market impact

November 30, 2022

By Joe Davis Sponsored by France’s ElectroniqueS magazine, the Electrons d’Or Award program identifies the most innovative products of the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Struggling to verify the reliability of your multiple-power-domain designs?

November 21, 2022

By Hossam Sarhan With the growing complexity of system-on-chip designs and technology scaling, multiple power domains are needed to optimize...

By Calibre IC Design & Manufacturing

< 1 MIN READ

TSMC OIP Ecosystem Forum 2022 all wrapped up, but not gone yet...

November 17, 2022

By Calibre Design Staff 1500+ attendees! 50 technical papers (30 live, 20 online) in three separate tracks! Standing room only...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Efinix Titanium FPGAs depend on mPower power integrity analysis

November 15, 2022

By John Wagnon Efinix’s high-performance Titanium FPGAs are custom-tailored for the computing demands of mainstream applications, targeting markets from intelligent...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Plug and Play ESD protection

November 9, 2022

By Mark Tawfik Electrostatic discharge (ESD) is the discharge of static electrical current when two objects come into contact. One...

By Calibre IC Design & Manufacturing

< 1 MIN READ

AUA announces extension of collaboration with Siemens for advanced research and academic enhancement

October 31, 2022

Back in 2012, the American University of Armenia (AUA) initiated a collaborative relationship with electronic design automation (EDA) leader Mentor...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Google, AMD, and Siemens EDA walk into a cloud…

October 10, 2022

By Michael White At DAC this past July, I had the opportunity to sit down with Phil Steinke from AMD...

By Calibre IC Design & Manufacturing

< 1 MIN READ

What’s an ESD design window, and why do I care?

October 6, 2022

By Derong Yan As we move to advanced semiconductor process nodes, electrostatic discharge (ESD) issues have become more critical in...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Can you spot the difference?

September 27, 2022

By James Paris We’ve all played those “Spot the Difference” games where you look at two similar images and try...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Outta my way – electrons coming through!

September 7, 2022

By Joel Mercier and Karen Chow Ever been in a hurry to get to a meeting, but there were a...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Papers and posters and prizes…oh my! Siemens EDA at DAC59!

August 22, 2022

By Shelly Stalnaker The Design Automation Conference of 2022 has come to an end. As the dust settles, and the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Custom & digital layout designers…Use the Calibre RealTime Platform to close DRC fixes faster.

August 8, 2022

By Srinivas Velivala Douglas Adams, who wrote The Hitchhiker’s Guide to the Galaxy, once said of deadlines, “I love deadlines....

By Calibre IC Design & Manufacturing

< 1 MIN READ

LVS Zero to Hero in 3 Easy Steps

August 3, 2022

By James Paris When it comes to system-on-chip (SoC) physical verification turnaround-time, layout vs. schematic (LVS) verification can make or...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Improve your layout load time without capital investment?

July 26, 2022

By Roger Kang How many times has this happened to you—you waited for an hour to complete the loading of...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Direct write DEF is DEFinitely the way to go for DFM back-annotation

July 18, 2022

By Armen Asatryan, James Paris DFM back-annotation to P&R Back-annotation of DFM changes to P&R databases can be a pain....

By Calibre IC Design & Manufacturing

< 1 MIN READ

Interactive symmetry checking for analog/custom ICs: Faster, easier, more accurate

July 6, 2022

By Sara Khalaf While the reliability and performance of multiple types of designs such as analog, MEMs, and image sensors...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Optimizing design implementation with Calibre LEF/DEF technology

June 22, 2022

By James Paris and Armen Asatryan Ever hear the saying “When all you have is a hammer, everything looks like...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Curves ahead for IC manufacturing

June 20, 2022

By John Sturtevant It turns out that the ideal mask pattern to print such a circle is in fact a...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Building the bridge between GDS and OASIS

June 13, 2022

By Shelly Stalnaker Switching from GDS to OASIS format can bring a host of benefits, but only if you make...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Does your parasitic extraction work in 5G IC designs?

June 6, 2022

By Salma Ahmed and Karen Chow The next-generation 5G mobile communication network is a heterogeneous network providing significant performance advantages...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A touchy subject: RF IC layout verification

May 24, 2022

By Neel Natekar Radio frequency (RF) circuitry is an essential component of many of the critical applications we now rely...

By Calibre IC Design & Manufacturing

< 1 MIN READ

The mPower toolsuite wins Elektronik Product of the Year for Software Tools!!

May 12, 2022

By Shelly Stalnaker Every year, the editors of Elektronik in Germany compile a list of the most interesting and innovative...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Smoothing the path to manufacturing success begins with CMP simulation and fill optimization

May 11, 2022

By Ruben Ghulghazaryan, Davit Piliposyan, Zhengfang Liu, Chunshan Du, Jeff Wilson, Qijian Wan, Xinyi Hu, Zhixi Chen Chemical-mechanical polishing (CMP)...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How to get to Win-Win-Win in conflict management

May 2, 2022

By Shelly Stalnaker & Calibre Design staff Anyone who’s been through conflict management training understands the three basic scenarios. There’s...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Innovations in physical verification tools and technologies keep the IC industry moving forward

April 20, 2022

By John Ferguson A few years ago, I was invited to present a paper discussing the advances in physical verification...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Using machine learning to improve DFM: a case study

April 12, 2022

By Ruben Ghulghazaryan, Davit Piliposyan, Misak Shoyan Several years ago, the American University of Armenia (AUA) and Siemens EDA began...

By Calibre IC Design & Manufacturing

< 1 MIN READ

The path of least resistance…leads to more reliable designs

April 6, 2022

By Derong Yan Meeting tapeout schedules and performance requirements are equally critical conditions for IC design success. Now engineers can...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Mastering RF design challenges: The role of capacitors and context-aware PEX Tools

April 4, 2022

By Claudia Relyea and Sandeep Koranne Updated January 17, 2025 The increasing complexity of modern RF circuits demands precise modeling...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Accelerating IC design time to market with Calibre in the cloud

March 31, 2022

By Michael White When you’re flying, it’s fun to look out the window and see clouds from “the other side.”...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Ease on down the road…why “ease of use” is the next big thing in EDA, and how we get there

March 16, 2022

Ease of use is an important issue when enhancing product functionality and introducing new technology. Calibre Design Systems considers ease...

By Calibre IC Design & Manufacturing

< 1 MIN READ

DRC voltage text annotations: Manually placed texts can be wrong!

March 14, 2022

By Abdellah Bakhali System-on-chip (SoC) designs often use multiple intellectual property (IP) blocks from multiple IP providers. Each IP provider...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Do you trust the reliability of your 2.5D/3D IC package designs?

March 9, 2022

By Dina Medhat 2.5D/3D ICs have become an innovative solution for many design and integration challenges. Basic physical verification for...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Reliability checking for memory circuit design doesn’t have to destroy your eyesight!

March 7, 2022

By Hossam Sarhan Memory blocks contain sensitive analog circuits that are crucial for the proper functionality of the whole design....

By Calibre IC Design & Manufacturing

< 1 MIN READ

DAC in December?? A Review of Calibre Design Solutions at DAC 2021

March 3, 2022

Did it feel a bit weird to be submitting research papers for DAC 2022 while packing to go to DAC...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

February 28, 2022

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point...

By Calibre IC Design & Manufacturing

< 1 MIN READ

The “next” technology node: ready or not, here it comes

February 22, 2022

By Shelly Stalnaker For years, decades even, the semiconductor industry has lived by the process node, which was originally named...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Physical design engineers…Learn the secret to generating signoff fill in P&R and accelerating your tapeouts

February 21, 2022

By Srinivas Velivala Place and route (P&R) engineers are always on the lookout for ways to optimize their design flows...

By Calibre IC Design & Manufacturing

< 1 MIN READ

IC package designers—looking for multi-die, system-level signoff verification?

February 16, 2022

By Shelly Stalnaker Ever tried a food sample when you were shopping…not just because it’s free food (!), but because...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Stronger together! Context-aware SPICE simulation combines the strengths of static and dynamic verification for faster, more precise full-chip ESD verification

January 31, 2022

By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Package verification just took a big step forward…

January 18, 2022

By Armen Asatryan and John Ferguson Over a decade ago, Calibre Design Solutions moved early into defining and building physical...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Coding for maximum performance and efficiency

January 11, 2022

A great software program does much, much more than just execute routines. It also optimizes the use of CPU resources...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre Design Solutions takes a look back at 2021

January 4, 2022

Okay, is everyone ready for an end-of-year wrapup? It’s certainly been an eventful 2021 for Calibre Design Solutions, even if...

By Calibre IC Design & Manufacturing

< 1 MIN READ

The most interesting man in EDA…

December 21, 2021

As the calendar year comes to a close, we face the prospect of saying goodbye to someone who has been...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre Design Solutions at Samsung SAFE Forum: technology leadership through innovation, intelligence, and integration

December 15, 2021

Since 2018, Samsung Foundry has operated their foundry ecosystem program, called SAFE™ (Samsung Advanced Foundry Ecosystem), to ensure deep collaboration...

By Calibre IC Design & Manufacturing

< 1 MIN READ

mPower power integrity analysis solution certified by Tower Semiconductor for advanced analog process technologies

December 8, 2021

The Siemens mPower power integrity solution, the first and only IC power integrity analysis solution that provides virtually unlimited scalability...

By Calibre IC Design & Manufacturing

< 1 MIN READ

TSMC OIP Forum celebrates collaboration and innovation…and we have the awards to prove it!

November 29, 2021

TSMC’s Open Innovation Platform® (OIP) brings together the creative thinking of customers and partners with the common goal of shortening...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Samsung Foundry and Siemens EDA: Helping companies design the next generation of Performance Platforms 2.0

November 9, 2021

Since 2018, the Samsung Advanced Foundry Ecosystem (SAFE™) program has encouraged and supported deep collaboration between Samsung Foundry and its...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Want to know what went on at the TSMC OIP Forum this year? Here’s the inside scoop…

November 3, 2021

TSMC customers and partners always look forward to the annual TSMC Open Innovation Platform® (OIP) Forums. Here, they get the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Fix first, finish faster!

October 28, 2021

By James Paris A few years ago, I came across some plans to build a simple bookshelf that would fit...

By Calibre IC Design & Manufacturing

< 1 MIN READ

In the EDA world, efficiency + ease of use = productivity (and profitability!)

October 21, 2021

By Shelly Stalnaker Electronic design automation (EDA) grew out of the need to make it easier and faster to design...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Cloud Computing Makes Overnight TAT Attainable

October 11, 2021

By Matthew Hogan and Derong Yan As we all know, during the final sign-off verifications of full chip system-on-chip (SoC)...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Companies talk about how mPower enables their tape-out success

September 30, 2021

By Joe Davis Earlier this week, we introduced our new mPower product line for power integrity signoff analysis. Our innovative...

By Calibre IC Design & Manufacturing

< 1 MIN READ

We know…power integrity analysis can be a really big pain, especially for really big designs

September 28, 2021

By Joe Davis Design teams use power integrity analysis to determine if the circuits in their designs will provide the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Don’t like standing in lines? Get with the (right) programs!

September 24, 2021

By John Ferguson For a while, it appeared that the worst of the COVID pandemic was behind us. My mind...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Get rid of GUI frustration and speed up your Calibre verification job submissions!

September 14, 2021

By Slava Zhuchenya Graphical user interface (GUI) frustration is real. Deployment of integrated circuit (IC) physical and circuit verification decks...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Seeing is believing (and learning)…

August 23, 2021

Are you a visual learner? Lots of folks are—they understand and retain instructions much more easily when they can watch...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Caution! Avoid detours when improving resistance on ESD paths

August 19, 2021

By Derong Yan As overall transistor dimensions shrink, integrated circuit (IC) chip designs become more sensitive to the damage caused...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Custom layout designers…Want to know a secret? You can close DRC faster. A lot faster…

August 16, 2021

By Srinivas Velivala Design rule checking (DRC) closure is a “tax” that custom layout designers must pay at all process...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Can we just agree that perception is everything? Especially in IC design?

August 4, 2021

By Dennis Joseph Is the dress black and blue, or white and gold? Is that a rabbit or a duck?...

By Calibre IC Design & Manufacturing

< 1 MIN READ

2.5/3D IC designers! Don’t get hung up on latch-up!

July 27, 2021

By Dina Medhat Latch-up is modeled as a short circuit (low-impedance path) that occurs in an integrated circuit (IC). It...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Don’t hit a roadblock in automotive electronics reliability verification!

July 21, 2021

The recent surge in used car prices may have you wondering what is driving this upswing, and just how much...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Efficient package delivery is not just for FedEx!

July 12, 2021

By John Ferguson Cost, risk, and the limitations of monolithic scaling are driving growth in multi-die (heterogeneous) advanced IC packaging...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Do you need an automated ESD verification methodology for 2.5D/3D ICs? If so, read on…

July 8, 2021

By Dina Medhat Electrostatic discharge (ESD) events cause severe damage to unprotected integrated circuits (ICs). You already know that, of...

By Calibre IC Design & Manufacturing

< 1 MIN READ

P&R engineers! Interested in saving (LOTS of) time in your tapeout schedules?

June 28, 2021

By Srinivas Velivala As a P&R engineer, you probably spend lots of time 1) waiting for batch DRC runs to...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Time is money…so why waste it on bad data?

June 21, 2021

By James Paris Last Saturday was my son’s birthday and we had many things to do to get ready for...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Shining a light on silicon photonics verification

June 14, 2021

By John Ferguson, Omar ElSewefy, Nermeen Hossam, Basma Serry We’re all fascinated by light. Light beams shooting from aliens’ eyes,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

ESD protection verification in 2.5/3D ICs is HARD (or is it?) Our on-demand webinar has the answer

June 7, 2021

By Calibre Staff Electrostatic discharge (ESD) is a big worry for integrated circuit (IC) designers, for good reason. A bit...

By Calibre IC Design & Manufacturing

< 1 MIN READ

SAFE is good. SAFE awards are even better…

June 1, 2021

By Calibre staff Safe is good, right? We all want to be safe, especially these days. But safe took on...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Turn IC verification challenge from a hard slog into a walk in the park by using static checks

May 19, 2021

By Neel Natekar As integrated circuits (ICs) grow in complexity, they create new challenges for IC verification flows and electronic...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A SAMPle of what you need to know about SAMP technology

May 13, 2021

By Calibre Design Staff Prior to the availability of extreme ultraviolet (EUV) lithography, multi-patterning provided the only workable yield solution...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Realize Live + U2U: Side by Side

May 4, 2021

What a difference a year can make! Oh, we’re not referring to that virus that shifted the Earth on its...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Give me my space! Why high voltage and multiple power domain designs need automated context-aware spacing checks

April 20, 2021

By Sherif Hany and Abdellah Bakhali Regardless of which technology node they’re using, design houses that create high-voltage and multiple...

By Calibre IC Design & Manufacturing

< 1 MIN READ

DFM: Still a really good thing to do!

April 14, 2021

By Simon Favre If you’re not using critical area analysis and design for manufacturing to improve your IC yield and...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Collaboration and innovation thrive on diversity

April 5, 2021

Back in November 2019, just a few short months before we all began an enforced year of isolation and separation,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

What is critical area analysis and why should I care?

April 1, 2021

By Simon Favre What makes money in the semiconductor industry? A killer IC design? Something so innovative that it blows...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Adaptive Patterning: Moving with the times (and technologies)

March 24, 2021

By John Ferguson and Kevin Rinebold Deca Technologies’ Adaptive Patterning technology and their newly-announced adaptive patterning design kit (APDK) have...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Building a strong reliability foundation with Calibre PERC

March 9, 2021

By Matthew Hogan How are you handling your reliability verification right now? Custom reliability verification? No reliability verification? How confident...

By Calibre IC Design & Manufacturing

< 1 MIN READ

SPIE-ing at a distance…

March 3, 2021

The SPIE Advanced Lithography Digital Forum took place Feb 22-26, and of course, Siemens EDA was there! We wouldn’t miss...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Early circuit verification can get you to tapeout faster…here’s how

February 4, 2021

For the last few years, it’s been hard to see design teams struggling to meet tapeout schedules caused by increasing...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Automated ESD protection verification for 2.5-3D ICs is now a reality

January 28, 2021

Got the mid-winter blahs? The post-New Year letdown? Looking for something to rev you up? How about an automated method...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Stochasticity of the input current is an important factor in accurate EM assessment for on-chip power delivery networks

January 18, 2021

At every conference, there is always that anticipatory moment just before the coveted “Best Paper” awards are announced. After all,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

2021: Time to simplify your life (or at least your workload)?

January 14, 2021

Everyone makes resolutions for a better life at the start of a new year – why not resolve to make...

By Calibre IC Design & Manufacturing

< 1 MIN READ

GLOBALFOUNDRIES and Mentor Launch a New Innovative DRC+ Hotspot Solution using Machine Learning in Calibre

December 9, 2020

By Shelly Stalnaker – Mentor, A Siemens Business I recently had the chance to attend an on-demand webinar introducing the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Mentor receives 2020 TSMC OIP Partner of the Year awards for EDA solutions

November 30, 2020

By Shelly Stalnaker – Mentor, A Siemens Business While the structure of the TSMC OIP Ecosystem Forum had to change...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Verification run configurations stressing you out? Automate them!

November 12, 2020

By Srinivas Velivala – Mentor, A Siemens Business As all new IC verification engineers learn very quickly, there is far...

By Calibre IC Design & Manufacturing

< 1 MIN READ

SAFE at home! Attending the Samsung SAFE forum in 2020

October 22, 2020

By Shelly Stalnaker – Mentor, A Siemens Business Samsung is going virtual with their 2020 SAFE forum, and Mentor, a...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Do you have a reliable automated waiver process for reliability verification?

October 13, 2020

By Dina Medhat – Mentor, A Siemens Business Design rule waivers Maybe a design rule that made sense at 22nm...

By Calibre IC Design & Manufacturing

< 1 MIN READ

SAMP series finishes with SAMP cut mask decomposition techniques

September 9, 2020

By David Abercrombie and Rehab Kotb Ali – Mentor, A Siemens Business We’ve been writing about self-aligned multi-patterning (SAMP) topics...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Breaking it down…How interconnect segmentation helps resolve P2P resistance errors

August 12, 2020

By Slava Zhuchenya – Mentor, A Siemens Business Point-to-point (P2P) simulations find and report nets that exceed predefined resistance thresholds...

By Calibre IC Design & Manufacturing

< 1 MIN READ

VLSI optimization—a bridge too far?

August 12, 2020

source: Andrew Shiva/CC BY-SA 4.0By Sherif Hany – Mentor, A Siemens Business Job without end. How about job done? Have...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A better, faster, smarter way to insert filler cells in P&R

August 11, 2020

By Fady Fouad, Jeff Wilson, Esraa Swillam – Mentor, A Siemens Business Filler cells—Those cells inserted by the P&R tool...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Early-stage design verification slowing down your schedules? Watch our on-demand web seminar for the solution

August 4, 2020

You’re integrating your design. Some blocks are incomplete. Others just have placeholders. But you can’t wait until every component is...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Can you picture your EDA in the cloud?

July 13, 2020

Moving electronic design automation (EDA) design verification to the cloud—we’ve talked about it and written about it, but sometimes you...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Five white papers that could change your life…

July 7, 2020

By Shelly Stalnaker – Mentor, A Siemens Business Someone once said to me, “You don’t have to be smart to...

By Calibre IC Design & Manufacturing

< 1 MIN READ

The benefits of working together: AUA and Mentor celebrate their long-term collaboration

June 15, 2020

By Sedrak Sargisian – Mentor, A Siemens Business We recently had the privilege of hosting representatives from the American University...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Fixing DFM hotspots with Calibre signoff during design implementation

June 9, 2020

By Srinivas Velivala – Mentor, A Siemens Business Adding the Calibre RealTime Digital API to the GLOBALFOUNDRIES DFM-POP hotspot fixing...

By Calibre IC Design & Manufacturing

< 1 MIN READ

EDA in the cloud—your questions answered

June 1, 2020

By Michael White – Mentor, A Siemens Business EDA in the cloud…learn why the cloud has become a viable and...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Automated common resistance checking…it’s the smart thing to do!

May 20, 2020

By Hossam Sarhan – Mentor, A Siemens Business Work smarter, not harder. Isn’t that what everyone is always telling you?...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Automate via insertion for improved design reliability and performance

May 15, 2020

By Fady Fouad, Esraa Swillam, and Jeff Wilson – Mentor, A Siemens Business IR drop and EM issues slowing down...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Mentor, AMD, and Microsoft collaborate on EDA in the cloud

May 4, 2020

By Omar El-Sewefy – Mentor, A Siemens Business While cloud processing has been around for years, running integrated circuit (IC)...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Track decomposition for SAMP processes—What you need to know

April 21, 2020

By David Abercrombie and Rehab Kotb-Ali – Mentor, A Siemens Business Understanding key requirements and root causes of errors is...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Open letter to the IC design community

April 10, 2020

Joseph Sawicki – executive vice president, Mentor IC EDA Access free 30-Day On-Demand Training, plus webinars & knowledge content

By Calibre IC Design & Manufacturing

< 1 MIN READ

More data is better in P2P debugging

January 31, 2020

By Slava Zuchenya – Mentor, A Siemens Business P2P debugging taking too much time? Using Calibre RVE colormapping can help...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Getting to tapeout faster... and easier!

January 6, 2020

By Sherif Hany – Mentor, A Siemens Business Complex reliability checks blowing your verification schedule? Learn how Calibre PERC smart...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Do you trust your AI/ML chips?

December 17, 2019

By Neel Natekar – Mentor, A Siemens Business AI/ML chips are seeing growing adoption, but ensuring reliable operation and trusted...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Choosing a SAMP process at 5nm and below

December 9, 2019

By David Abercrombie, Rehab Kotb Ali, Ahmed Hamed-Fatehy – Mentor, A Siemens Business SADP, SAQP, and SALELE all have pros...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Partners help each other succeed…

December 4, 2019

At their recent Open Innovation Platform (OIP) Ecosystem Forum held in Santa Clara, CA, TSMC named Mentor as their OIP...

By Calibre IC Design & Manufacturing

< 1 MIN READ

MaxLinear and Calibre RealTime Digital in-design DRC: a winning combination

November 18, 2019

By Srinivas Velivala – Mentor, A Siemens Business MaxLinear implemented the Calibre RealTime Digital interface for fast, iterative signoff DRC...

By Calibre IC Design & Manufacturing

< 1 MIN READ

SRAM quality vs. flexibility: it’s a high-wire balancing act

November 13, 2019

By Elven Huang – Mentor, A Siemens Business SRAM debugging at advanced nodes is challenging. With pattern matching and similarity...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Do you have all the data required for HDAP LVS? Not sure? That’s okay!

October 29, 2019

By Tarek Ramadan – Mentor, A Siemens Business Automated LVS/LVL verification for HDAP isn’t quite a mature process yet, but...

By Calibre IC Design & Manufacturing

< 1 MIN READ

SoC IO ring checking: going beyond ESD verification

October 22, 2019

By Abdellah Bakhali – Mentor, A Siemens Business Better SoC IO ring verification means more accurate and consistent product reliability....

By Calibre IC Design & Manufacturing

< 1 MIN READ

Thrive and survive with Calibre in the Cloud

October 15, 2019

We recently participated in a presentation discussing something that is certainly creating a significant impact these days… Read more about...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How to be a hero in LVS debug

October 8, 2019

By Raghav Katoch, Mentor – a Siemens business LVS debug got you down? Stuck at your desk trying to resolve...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre RealTime Digital interface scores a Finalist spot in the 2019 Elektra Awards

September 30, 2019

Since 1960, Electronics Weekly has provided the most up-to-date and insightful news, commentary, and analysis to electronics industry professionals all...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Where today meets tomorrow…

September 25, 2019

On September 4, 2019, Siemens PLM Software officially became Siemens Digital Industries Software. As the rate of innovation increases, and...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Want a better, faster way to write reliability rules and checks? Try an XML constraint file!

August 30, 2019

By Dina Medhat – Mentor, A Siemens Business XML constraint files are the better, faster way to define Calibre PERC...

By Calibre IC Design & Manufacturing

< 1 MIN READ

SoC integration issues? Now you can find them earlier, and fix them faster

August 13, 2019

By Nermeen Hossam and John Ferguson – Mentor, A Siemens Business Our Calibre Recon tool helps SoC teams quickly find...

By Calibre IC Design & Manufacturing

< 1 MIN READ

That cloud looks like…a successful IC tapeout!

August 5, 2019

By Omar El-Sewefy – Mentor, A Siemens Business Running Calibre software in the cloud can help companies quickly adjust resource...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Inductance parasitics: the enemy of analog/RF performance and reliability

July 18, 2019

By Hossam Sarhan – Mentor, A Siemens Business Ignoring interconnect inductance extraction in analog and RC designs can be a...

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Samsung and Mentor getting headlines with innovative fast LFD using machine learning

July 11, 2019

By Shelly Stalnaker – Mentor, A Siemens Business Tom Dillinger, editor at SemiWiki, recently attended the Samsung Foundry technology forum...

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Optimize design databases by deleting duplicate data

July 9, 2019

By James Paris – Mentor, A Siemens Business Are you suffering from data inefficiency? Learn how you can remove data...

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Automated full-chip ESD protection verification is here!

June 21, 2019

By Frank Feng – Mentor, A Siemens Business Full-chip ESD verification can be challenging, especially at advanced nodes. Adopting logic-driven,...

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Stronger, better, earlier latch-up protection? Yes, please!

June 14, 2019

By Flint Yoder – Mentor, A Siemens Business Tight schedules? Worried about product reliability? Now you can find and eliminate...

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Focus on this…Faster, more accurate litho hotspot detection with machine learning

June 7, 2019

By Wael ElManhawy and Joe Kwan – Mentor, A Siemens Business Faster, more accurate lithographic hotspot detection with fast LFD...

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Calibre in the Cloud

May 22, 2019

While the practice of using cloud resources to run software jobs is certainly not new, its use for EDA tool...

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Today’s ERC demands new verification capabilities to ensure product reliability and performance

May 8, 2019

By Derong Yan – Mentor, A Siemens Business Today’s advanced ERC requires an EDA tool that can automatically understand complex...

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Sharpening your focus…Removing irrelevant data during P2P debugging

April 22, 2019

By Slava Zhuchenya – Mentor, A Siemens Business Want to minimize resource and load times, while improving P2P resistance debugging?...

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Sometimes you just want less – Splitting IC layouts saves time and resources

April 16, 2019

By Dennis Joseph – Mentor, A Siemens Business One slice instead of the whole pizza. One single 1¼“ nail, not...

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Packaging custom checks standardizes and simplifies reliability verification

April 10, 2019

By Hossam Sarhan, Mentor – A Siemens Business Using a packaged checks flow lets designers quickly select, configure and run...

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The power of innovation: Letting patterns create themselves with self-aligned multi-patterning

April 5, 2019

By David Abercrombie, Rehab Kotb Ali, Ahmed Hamed-Fatehy – Mentor, A Siemens Business Given the alignment control issues in traditional litho-etch...

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3D InCites community awards Mentor, a Siemens Business “EDA Provider of the Year” for 3rd consecutive year!

March 13, 2019

Every year, 3D InCites, an online media resource dedicated to all things 3D in the semiconductor industry, recognizes company and...

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Context-aware verification checks enhance checking and debugging capabilities

February 15, 2019

By Sherif Hany – Mentor, A Siemens Business Automated context-aware verification helps designers ensure the performance and reliability of complex...

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Silicon photonics design and verification joining the mainstream

February 5, 2019

By John Ferguson – Mentor, A Siemens Business Silicon photonics offers up the promise of blazing fast data transmission and...

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Lane ends—full-chip merge ahead

January 21, 2019

By James Paris – Mentor, A Siemens Business Fast layout merging during continuous build flows makes it easier to solve...

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Simplify your life with Calibre RVE filters!

January 14, 2019

Sometimes there are simply too many choices in life. Who needs 35 flavors of juice, or 20 different hammers? Having...

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Vroom! Vroom! Getting to the tapeout finish line faster…

January 3, 2019

By Srinivas Velivala – Mentor, A Siemens Business The Calibre RealTime Digital interface helped Qualcomm spend less time fixing DRC...

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High voltage and multiple power domain designs need a little TLC (and automated VA-DRC)

December 17, 2018

By Sherif Hany – Mentor, A Siemens Business High-voltage and multiple power domain applications demand high reliability. Calibre PERC enhanced...

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What is critical area analysis and why should I care?

December 12, 2018

By Simon Favre – Mentor, A Siemens Business Have you ever wondered what critical area analysis can do for you?...

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Back to the future (or how to solve problems before they exist)

December 4, 2018

By Ruben Ghulgazaryan, JinHee Kim, Jeff Wilson – Mentor, A Siemens Business Foundries and design companies working together in a...

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Whither goest 3D-IC?

November 27, 2018

By John Ferguson – Mentor, A Siemens Business Assembly-level design kits may be a critical factor in the emergence of...

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When is a DRC error not an error?

November 19, 2018

By John Ferguson – Mentor, A Siemens Business Error waivers are the dark matter of IC verification—they cancel out DRC...

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The best things come in small packages

November 13, 2018

By John Ferguson – Mentor, A Siemens Business Do you know what the three challenges of HDAP design are? Are...

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Eye charts aren’t the answer to analog design reliability…

November 6, 2018

By Hossam Sarhan and Alexandre Arriordaz – Mentor, A Siemens Business Adding Calibre PERC automated reliability checks to the analog...

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Apples, oranges, pears, and lemons…comparing rule-based PEX to field solver results can be fruitless if you’re not careful

October 30, 2018

By Yousry ElMaghraby – Mentor, A Siemens Business Need to validate your rule-based PEX against a field solver solution? Better...

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It’s okay to be pushy!

October 23, 2018

By James Paris – Mentor, A Siemens Business Get the full benefit of parallel design implementation by pushing block-level contextual...

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Here’s a set of candidates everyone can support!

October 16, 2018

By Wael ElManhawy – Mentor, A Siemens Business Do you debug sub-20nm layouts? Want to make your life easier? Adopt...

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Shocking news! HDAPs need system-level electrical analysis to ensure performance

October 9, 2018

By Tarek Ramadan – Mentor, A Siemens Business As the use of HDAP grows, so does the need for post-layout...

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Fixing DRC errors in SADP designs at sign-off—Nobody said it was easy (but it can be easier…and much faster)

October 2, 2018

By David Abercrombie – Mentor, A Siemens Business SADP + DRC = headaches? Not any longer. GLOBALFOUNDRIES and Mentor collaborated...

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A look at what's to come at OIP (hint: we'll be there!)

September 28, 2018

The 2018 TSMC Open Innovation Platform® (OIP) Ecosystem Forum in Santa Clara starts this Wednesday, October 3rd! As usual, Mentor...

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Fractures aren’t always a bad thing…especially in resistance extraction

September 24, 2018

By Hossam Sarhan – Mentor, A Siemens Business Did you know? IC designs that use unconventional metal structures with multiple...

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A brief history of the process design kit

September 19, 2018

By John Ferguson – Mentor, A Siemens Business Do you really know what goes into a PDK? You might be...

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Get rid of pesky parasitics fast!

September 11, 2018

By Karen Chow and Claudia Relyea – Mentor, A Siemens Business Parasitics hampering the performance of your advanced node or...

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Do you trust your reliability baseline? Well, do you?

September 4, 2018

By Matthew Hogan – Mentor, A Siemens Business Custom reliability verification? No reliability verification? Foundry-qualified reliability rule decks provide an...

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< 1 MIN READ

Did you know the Calibre PERC platform has an automated waivers functionality?

August 20, 2018

By Dina Medhat – Mentor, A Siemens Business Want to waive complex reliability conditions? Manage multiple users waiving results...

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P&R Designers—Want to quickly analyze and debug signoff DRC errors in P&R?

August 8, 2018

By Srinivas Velivala – Mentor, A Siemens Business Want a better, faster way to debug signoff DRC errors in P&R?...

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Pssst, digital designers…wanna save WEEKS on your tapeouts?

August 2, 2018

By Srinivas Velivala – Mentor, A Siemens Business Who doesn’t want to save weeks of precious time on their tapeouts...

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DFM never stopped being a really good thing to do

July 25, 2018

By Simon Favre – Mentor, A Siemens Business If you’re not using critical area analysis and design for manufacturing to...

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Announcing Calibre RealTime Digital launch - with presentations at DAC!

June 19, 2018

Mentor has launched a new product – Calibre RealTime Digital!

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Calibre at DAC - What you won't want to miss!

June 12, 2018

Design Automation Conference (DAC) is always full of exciting activities with lots of opportunities to learn – and this year...

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Silicon Photonics Verification: A Light in the Tunnel

May 31, 2018

By Omar El-Sewefy – Mentor, A Siemens Business Do silicon photonics designs need new verification tools? Turns out, expanding established...

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Standing on the corner, waiting for my layout to load…

May 21, 2018

By Dennis Joseph – Mentor, A Siemens Business Ever had this happen? You start loading your GDS layout and go...

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Customizing a Calibre DRC HTML Report

April 26, 2018

Love the DRC HTML report you can generate with a push of a button from Calibre interface tools, but wish...

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P&R Designers— How to quickly analyze and debug signoff DRC errors in P&R, using the Calibre RVE interface

April 10, 2018

Want to quickly analyze and debug signoff DRC errors in P&R? The Calibre RVE multi-viewer function lets you sync multiple...

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IC designers: find your focus and priorities during DRC debug

April 5, 2018

By Srinivas Velivala – Mentor, A Siemens Business Layout design verification gets exponentially harder with each new process technology node....

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Highlights from SPIE - Successes and advancements over the past year

March 8, 2018

By Gandharv Bhatara – Mentor, A Siemens Business At the 43rd SPIE Advanced Lithography conference in San Jose that ran from...

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Calibre PERC electrical reliability verification – why you need it at every node

March 5, 2018

By Juan C. Rey, Vice President of Engineering, Calibre – Mentor, A Siemens Business If you’re not performing electrical reliability...

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< 1 MIN READ

Watch & Learn: Reducing Time-to-Support

February 26, 2018

By Srinivas Velivala – Mentor, A Siemens Business If you’re a chip designer or a CAD person trying to figure...

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Simplify and speed up early floorplan verification with incremental interface DRC

February 13, 2018

By James Paris – Mentor, A Siemens Business In early floorplan verification, incomplete blocks produce numerous interface errors. Incremental interface...

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Establishing a reliability baseline provides confidence and consistency

February 6, 2018

By Matthew Hogan – Mentor, A Siemens Business Design companies must establish baseline robustness and reliability criteria throughout the entire...

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Get to yield ramp faster…even with new design styles

January 30, 2018

By Wael Manhawy and Joe Kwan – Mentor, A Siemens Business Having trouble ramping yield for new, unproven design styles? Experiments...

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HDAP connectivity verification—what’s your solution?

January 23, 2018

By Tarek Ramadan – Mentor, A Siemens Business New HDAP designs like FO-WLP require package-level connectivity verification tools and processes....

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What's New in Multi-Patterning?

January 17, 2018

If you work with multi-patterning technology, you know it is a constantly-evolving process. From the addition of new multi-patterning techniques...

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Tiny Chips, Big Challenges: Full-Chip Electrical Reliability

January 9, 2018

Need to ensure your chip performs in the real world? The Calibre PERC reliability platform provides fast, accurate, verification for...

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Can machine learning and neural networks accurately predict post-deposition profiles for CMP modeling?

January 3, 2018

By Ruben Ghulghazaryan and Jeff Wilson – Mentor, A Siemens Business We experimented with machine learning and neural networks for...

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Waiver headaches? We have a cure for that…

December 27, 2017

By James Paris – Mentor, A Siemens Business Creating a standardized IP waivers database to deliver with physical IP libraries...

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SRAM physical verification – Why does it have to be so hard? (Hint: it doesn’t)

December 19, 2017

By James Paris and Elven Huang – Mentor, A Siemens Business Checking SRAM IP placements can be tricky, even for...

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Does this color look good on me?

December 12, 2017

By David Abercrombie and Alex Pearson – Mentor, A Siemens Business Any given layout has multiple coloring configurations that pass...

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Want improved design optimization? Try integrating pattern matching with DFM properties

December 4, 2017

By Sherif Hany, Mentor – A Siemens Business Integrating pattern matching with DFM operations ensures designs are quickly and accurately...

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How to optimize performance during physical verification

November 27, 2017

By John Ferguson – Mentor, A Siemens Business Are you getting the most from your processes, tools, and hardware? Or...

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Do my database merges make my runtimes too slow?

November 20, 2017

By Saunder Peng – Mentor, A Siemens Business Merging databases often creates bottlenecks in the design and verification flow, wasting...

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Shocking news about ESD protection!

November 14, 2017

By Derong Yan – Mentor, A Siemens Business Electrostatic discharge (ESD) protection is critical for today’s electronic products, which require...

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Using Body Bias in High Performance, Low Power Electronics

October 17, 2017

By Flint Yoder – Mentor, A Siemens Business The body bias effect is used to tune circuit behavior to meet...

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The Chicken or the Egg? Finding Litho Hotspots Before Design Rules Exist

September 25, 2017

By Wael ElManhawy and Joe Kwan – Mentor, A Siemens Business Which comes first, accurate design rules or real designs?...

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Now You See Them…Now You Don’t: Recognizing DP Errors at Advanced Nodes

September 18, 2017

By David Abercrombie and Alex Pearson – Mentor, A Siemens Business At advanced nodes, designers need enhanced error visualization and...

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Calibre Collaboration and Innovation on Display at TSMC OIP Santa Clara

September 15, 2017

At the TSMC Open Innovation Platform® (OIP) event in Santa Clara on September 13, Mentor was privileged to co-present with...

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GIGO, or Why Data Integrity Matters

September 11, 2017

By James Paris – Mentor, A Siemens Business Design data integrity is crucial to both product quality and tapeout schedules....

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Node Migration—What Does it Really Cost You?

September 1, 2017

By John Ferguson – Mentor, A Siemens Business Deciding when and how to make a process node transition is critical...

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CMP Modeling: Improving Manufacturing Results during Design

August 28, 2017

By Jeff Wilson and Ruben Ghulghazaryan – Mentor, A Siemens Business Accurate CMP models and simulation are crucial to both design process...

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< 1 MIN READ

The Speed of Reliability

August 22, 2017

By Dina Medhat – Mentor, A Siemens Business Electrical overstress (EOS) can damage or destroy an IC. The Calibre PERC...

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No Compromise: Fast, Accurate Parasitic Extraction at Advanced Nodes

August 14, 2017

By Chris Clee – Mentor, A Siemens Business Calibre’s innovative hybrid approach to parasitic extraction can solve your PEX challenges...

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In-Design Signoff DRC: Not Just a Dream

July 25, 2017

By Srinivas Velivala – Mentor, A Siemens Business Are you a custom or analog/mixed signal (AMS) designer? How often do...

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Searching for Latch-up in All the Right Places

July 17, 2017

By Matthew Hogan – Mentor, A Siemens Business While any error in a layout could be deemed unintentional (I mean, who...

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< 1 MIN READ

Take the Risk out of Signoff with Calibre YieldEnhancer Chip Polishing

July 10, 2017

By Bill Graupp – Mentor, A Siemens Business Designing integrated circuits (ICs) today is a complex and high-risk endeavor…

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Okay, I released my design to the fab, now what? Design to Mask – Part 2

July 5, 2017

By Minghui Fan – Mentor, a Siemens Business Managing the computational demands of today’s OPC and RET takes a dedicated...

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What does physical verification need today?

June 1, 2017

By Juan Rey – Mentor, A Siemens Business

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Good news – we’re at IMS this year!

May 30, 2017

Are you an analog designer? If so, you know how sensitive high-frequency circuits can be to silicon substrate parasitics. You...

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2017 Will Be B-I-G

May 25, 2017

By Michael White – Mentor, A Siemens Business Trends, plans, and advice on what you can do to succeed.

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Calibre Evolves Constantly

May 17, 2017

By Mike Santarini – Mentor, A Siemens Business I find it truly amazing that despite the constantly changing tide in the...

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Why Do Open and Supported Interfaces Matter More Than Ever?

May 4, 2017

By Michael Buehler-Garcia, Senior Director, D2S Calibre Marketing – Mentor, A Siemens Business Tools must talk to each other as...

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Okay, I released my design to the fab, now what? Design to Mask – Part 1

April 21, 2017

By Minghui Fan, Mentor Graphics The design is finally sent to the fab, where it magically becomes real. Is it...

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Package it up!

April 14, 2017

By Tarek Ramadan, Mentor Graphics Uniting package design environments with SoC physical verification tools ensures the necessary co-design and verification...

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Mentor tools now certified on TSMC 12 FFC or 7 nm

April 10, 2017

Planning a design using TSMC’s new 12 FFC or 7 nm V1.0 processes? Good news, the entire Mentor Graphics Calibre...

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Clear your calendar - U2U is coming!

March 24, 2017

Take a look at what you’ll find at this year’s Mentor’s user group event located at the Santa Clara Marriott...

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< 1 MIN READ

Are You Wasting Your SRAM Memory Redundancy?

March 20, 2017

By Simon Favre, Mentor Graphics Want to know if your SRAM redundant memory elements are actually useful, or a waste...

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See you at TSMC 2017!

March 9, 2017

It’s that time of year again…

By Calibre IC Design & Manufacturing

< 1 MIN READ

ECO Fill Can Rescue Your SoC Tapeout Schedule

February 27, 2017

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and re-verify late-stage changes quickly, while...

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What to see at SPIE 2017

February 20, 2017

It is time again for the SPIE Advanced Lithography conference.

By Calibre IC Design & Manufacturing

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DFM Line-End Enhancement with Calibre Pattern Matching

January 31, 2017

Using Calibre Pattern Matching to add line-end extensions to a design is a simple way to improve yield and reliability,...

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How to choose LVS box flow

January 30, 2017

How do you decide which kind of LVS BOX flow makes sense for what you want to accomplish? Watch this...

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Will EUV Kill Multi-Patterning?

January 25, 2017

By David Abercrombie, Mentor Graphics Many people think EUV lithography means the end of multi-patterning. Do you?

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Creating an initial Hcell list for Calibre LVS jobs, using Calibre Interactive

January 23, 2017

Need an hcell list for your hierarchical design? You can use the Calibre Interactive tool to quickly and automatically create...

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Using Automated Pattern Matching For SRAM Physical Verification

January 17, 2017

By Elven Huang, Mentor Graphics Accurate SRAM IP verification can be tricky, but automated pattern matching can help.

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Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

January 16, 2017

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs.

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Are You (Really) Ready for Your Next Node?

January 11, 2017

By Michael White, Mentor Graphics Skipping nodes is gaining popularity, but it can bring some unexpected challenges. Are you prepared?

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How to use different Calibre versions for Calibre RealTime and signoff Calibre DRC/LVS jobs

January 10, 2017

In this How-To Video – learn how to run Calibre DRC and LVS jobs from a signoff Calibre version simultaneously...

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How to run multiple Calibre RealTime jobs using multiple rule-decks

January 3, 2017

Need to run multiple rule decks on an AMS design? The Calibre RealTime tool lets you do just that easily...

By Calibre IC Design & Manufacturing

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A Pattern of Success: Calibre Pattern Matching

December 21, 2016

Calibre Pattern Matching enables innovative DRC and other applications across all process nodes and designs.

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How to run Calibre PERC jobs using Calibre Interactive

December 20, 2016

Running Calibre PERC jobs from the Calibre Interactive interface tool only requires a few easy steps. Get the details in...

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How to include additional rule files in Calibre Interactive

December 14, 2016

Want to run custom checks simultaneously with signoff DRC? The Calibre Interactive interface lets you do just that. Learn how...

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A new path for analog design constraints verification

December 12, 2016

By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for reliability and performance.

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Mentor's Battle of the Photonic Bulge

December 8, 2016

By Mitch Heins If silicon photonics verification is a battle to be won, Mentor Graphics is on the front lines...

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How to classify unique DRC results in Calibre RVE

December 7, 2016

Activating the Shape Class property in your Calibre RVE tool setup allows you to classify and view errors that share...

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All Together Now: FOWLP in the Foundry

December 5, 2016

By John Ferguson, Mentor Graphics FOWLP design popularity is driving foundries to develop in-house FOWLP flows. How will that affect...

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How To Navigate Through OPC Simulation Results in Calibre WorkBench

December 1, 2016

Learn how to quickly and easily scan multiple layers of Calibre OPC simulation results in the Calibre RVE tool for...

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Fill/Cut Self-Aligned Double-Patterning

November 28, 2016

By David Abercrombie, Rehab Ali, Ahmed Hamed-Fatehy, and Shetha Nolke How the SID-SADP process affects your design decisions –

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Creating An Accurate FEOL CMP Model

November 21, 2016

By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid FEOL CMP modeling helps designers and foundries predict CMP hotspots in advanced...

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Transistor level ESD verification in large SoC designs

October 31, 2016

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help

By Calibre IC Design & Manufacturing

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Context-Aware Latch-up Checking

October 17, 2016

By Matthew Hogan, Mentor Graphics Latch-up detection is challenging. Learn how automated LUP checks help you find and eliminate LUP...

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The Pitfalls of Auto-Stitching in Double-Patterning

October 10, 2016

By David Abercrombie, Mentor Graphics Untimely DP stitching can cause more problems than it solves, that’s why strategic use is...

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Established Technology Nodes: The Most Popular Kid at the Dance

September 27, 2016

By Michael White, Mentor Graphics Established nodes have a lot of dancing left to do! Learn how and why new...

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Back-annotating DFM enhancements to place & route tools

September 19, 2016

By James Paris, Mentor Graphics Back-annotation of DFM enhancements to P&R simplifies iterations as designers close timing and physical verification

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Device Pin-Specific Property Extraction For Layout Simulation

September 14, 2016

By Phil Brooks, Mentor Graphics Can you accurately extract device pin-specific properties without creating phantom nets?

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Synthesis of Design Rules and Patterns

August 31, 2016

By Michael White, Mentor Graphics Integrating pattern matching with design verification and process development yields benefits at all nodes. Learn...

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Electromigration protection requires accurate interconnect modeling

August 22, 2016

By Karen Chow, Mentor Graphics Electromigration can destroy an IC before its time. Are your designs safe?

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Leveraging Reliability-Focused Foundry Rule Decks

August 12, 2016

By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you correct reliability issues while they...

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Pattern Matching In Test and Yield Analysis

August 1, 2016

By Jonathan Muirhead and Geir Eide, Mentor Graphics Analyzing fail data with pattern matching helps companies identify yield limiters faster...

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Reliability Scoring for the Automotive Market

July 18, 2016

By Jeff Wilson, Mentor Graphics Companies designing automotive electronics must understand how variability affects design quality and reliability.

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Not yet a fan of fan-out? Why you should be!

July 12, 2016

By John Ferguson, Mentor Graphics FO-WLP combines multiple die from heterogeneous processes into a compact package, and that’s a good...

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Interconnect Robustness Depends on Scaling for Reliability Analysis

June 29, 2016

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Pattern Matching in Design Verification

June 1, 2016

By Michael White, Mentor Graphics Automated pattern matching can solve a wide range of design verification issues. Are you in...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Efficient Parasitic Extraction Techniques for Full-Chip Verification

May 26, 2016

By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC design is essential. But how...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How Do I ECO a Multi-Patterned Design?

May 11, 2016

By David Abercrombie and Alex Pearson, Mentor Graphics Applying ECOs to multipatterned designs can be a nightmare, unless you plan...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Colorless vs. Colored Double-Patterning Design Flows

April 18, 2016

By David Abercrombie, Mentor Graphics How do you know which double patterning flow to use?

By Calibre IC Design & Manufacturing

< 1 MIN READ

Collaborative SoC Verification

April 11, 2016

By Matthew Hogan, Mentor Graphics The increasing use of SoC designs turns efficient IC design and validation into a team...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Reducing Post-Placement Leakage with Stress-Enhanced Fill Cells

April 5, 2016

By Valeriy Sukharev, Jun-Ho Choy, Armen Kteyan and Henrik Hovsepyan, Mentor Graphics Optimizing power usage for mobile devices at advanced...

By Calibre IC Design & Manufacturing

< 1 MIN READ

When and How Should I Color My DP Layout?

March 29, 2016

By David Abercrombie, Mentor Graphics Automated DP coloring solutions minimize DP errors. But when is the best time and how...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Parasitic Extraction for Accurate Signal Integrity Analysis at Advanced Nodes

March 15, 2016

By Karen Chow, Mentor Graphics Signal integrity analysis at advanced nodes requires new and enhanced parasitic extraction techniques

By Calibre IC Design & Manufacturing

< 1 MIN READ

Five Steps to Double Patterning Debug Sucess

March 2, 2016

By David Abercrombie, Mentor Graphics Shhhh…David Abercrombie’s revealing the secrets of successful DP debugging!

By Calibre IC Design & Manufacturing

< 1 MIN READ

Automated Power Model Verification for Analog IPs

February 23, 2016

By Sierene Aymen and Hartmut Marquardt, Mentor Graphics Eliminating manual work during power intent verification of analog IPs reduces susceptibility...

By Calibre IC Design & Manufacturing

< 1 MIN READ

More Than Moore: Finally Crossing the Chasm?

February 15, 2016

By Michael White, Mentor Graphics Will fan-out wafer-level packaging be the impetus that pushes 3D-IC into mainstream acceptance?

By Calibre IC Design & Manufacturing

< 1 MIN READ

An Automated Solution for Voltage-Aware DRC

February 2, 2016

By Dina Medhat, Mentor Graphics Automated voltage propagation with Calibre PERC makes it easier to comply with voltage-aware DRC spacing...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Resetting Expectations on Multi-Patterning Decomposition and Checking Part 2

January 25, 2016

By David Abercrombie, Mentor Graphics Triple and quadruple patterning can baffle even the most experienced designers. David Abercrombie has some...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Electromigration and IC Reliability Risk

January 19, 2016

By Dina Medhat, Mentor Graphics Gradual damage from electromigration can affect product performance and reduce product lifetimes. Reliability analysis ensures...

By Calibre IC Design & Manufacturing

< 1 MIN READ

You're Not Alone

January 12, 2016

By Srinivas Velivala, Mentor Graphics Calibre How-To videos replace your roadblocks with fast solutions for tricky verification problems

By Calibre IC Design & Manufacturing

< 1 MIN READ

Resetting Expectations on Multi-Patterning Decomposition and Checking

December 28, 2015

By David Abercrombie, Mentor Graphics Some common misconceptions about multi-patterning processes and just how they work.

By Calibre IC Design & Manufacturing

< 1 MIN READ

LEF/DEF IO Ring Check Automation

December 15, 2015

By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings…

By Calibre IC Design & Manufacturing

< 1 MIN READ

Correct by Construction and Other Myths

December 8, 2015

By Joseph Davis, Mentor Graphics Is “correct by construction” a myth?

By Calibre IC Design & Manufacturing

< 1 MIN READ

Why Do We Need Assembly Design Kits for Packages?

December 1, 2015

By John Ferguson and Tarek Ramadan, Mentor Graphics Why do we need assembly design kits for IC packages?

By Calibre IC Design & Manufacturing

< 1 MIN READ

Design Rule Checking for Silicon Photonics

November 17, 2015

By Ruping Cao, Mentor Graphics Verifying silicon photonics designs requires new techniques, like equation-based DRC

By Calibre IC Design & Manufacturing

< 1 MIN READ

Reported Death of Moore's Law Premature?

November 10, 2015

By Michael White, Mentor Graphics Is Moore’s Law dying? A look at the latest process node activity and technology

By Calibre IC Design & Manufacturing

< 1 MIN READ

Together At Last - Combining Netlist and Layout Data for Power-Aware Verification

November 3, 2015

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks on multiple-power-domain and mixed-signal designs...

By Calibre IC Design & Manufacturing

< 1 MIN READ

MEMS Technology and Manufacturing on the Microscale

October 27, 2015

By Carey Robertson and Khaled AbouZeid, Mentor Graphics Designers incorporating MEMS devices into high-volume CMOS ICs need new processes, data,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Deja Vu for CMP Modeling?

October 20, 2015

By Jeff Wilson, Mentor Graphics With manufacturing innovations and new DFM solutions, CMP modeling is gaining renewed popularity

By Calibre IC Design & Manufacturing

< 1 MIN READ

Assembly Design Kits are the Future of Package Design Verification

October 14, 2015

By John Ferguson, Mentor Graphics Like PDKs for ICs, qualified assembly design kits for packages can ensure the quality and...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Parasitic extraction for touchscreen designs

October 6, 2015

By Mohamed ElRefaee, Mentor Graphics Accurate parasitic extraction of touchscreens is essential for ensuring the high-quality performance the market demands

By Calibre IC Design & Manufacturing

< 1 MIN READ

Electrical Overstress Detection and Debugging

September 29, 2015

By Dina Medhat, Mentor Graphics Automated voltage propagation provides an accurate way to detect and correct those hard-to-find EOS conditions...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Case Studies in P&R Double Patterning Debug: Part Two

September 22, 2015

David Abercrombie continues his expert advice to P&R and chip finishing engineers on understanding and debugging multi-patterning errors accurately and...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Case Studies in Double-Patterning Debug: Part One

September 15, 2015

By David Abercrombie, Mentor Graphics Multi-patterning errors in P&R layouts can be intricate, and their solutions may not be obvious

By Calibre IC Design & Manufacturing

< 1 MIN READ

The Changing (and Challenging) IC Reliability Landscape

September 8, 2015

By Matthew Hogan, Mentor Graphics Reliability issues have gone way beyond DRC and LVS verification…

By Calibre IC Design & Manufacturing

< 1 MIN READ

The Fill Ecosystem Evolves Again

August 25, 2015

By Jeff Wilson, Mentor Graphics At 20nm, new fill constraints drive up the time and complexity of the fill process….

By Calibre IC Design & Manufacturing

< 1 MIN READ

Automate those voltage-dependent DRC checks!

August 18, 2015

By Beth Martin with Dina Medhat, Mentor Graphics What do all these new voltage-dependent DRC rules mean, and how do...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Video: ECO Fill Flow Framework

July 28, 2015

A video introduction to Mentor’s newly introduced utility called ecofill.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Extraction Challenges Grow in Advanced Nanometer IC Design

July 21, 2015

By Carey Robertson, Mentor Graphics The Calibre xACT platform is a new type of extraction tool that provides a range...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Automated Chip Polishing Can Make Your Design Shine

July 14, 2015

By Bill Graupp, Mentor Graphics A more robust design creates a more reliable product, and reduces yield variability over its...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Are Three Eyes Better Than Two?

July 7, 2015

By David Abercrombie, Mentor Graphics Error analysis in triple patterning is challenging, but a pyramid approach helps designers prioritize and...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Custom Layout Designers Need New Tools for New and Expanding Markets

July 1, 2015

By Srinivas Velivala, Mentor Graphics New debugging capabilities in Calibre RealTime can help shrink your time-to-tapeout while still ensuring high-quality...

By Calibre IC Design & Manufacturing

< 1 MIN READ

IoT, Cost-per-Transistor Extend Lifetimes of Established Technology Nodes

June 23, 2015

By Michael White, Mentor Graphics Much of the Internet of Things (IoT) functionality we crave is more cost-effective when implemented...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How Close Can We Put Different Voltage Regions Together?

June 16, 2015

By Joe Davis, Mentor Graphics Calibre tools provide a complete flow for implementing, optimizing, and verifying voltage-dependent layouts against the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Parasitic Extraction of FinFET-based Memory Cells

June 11, 2015

By Karen Chow, Mentor Graphics Accurate and efficient FinFET characterization requires a parasitic extraction tool that can apply different extraction...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Autonomous Systems and IC Reliability

June 2, 2015

By Matthew Hogan, Mentor Graphics New standards for IC quality and reliability verification

By Calibre IC Design & Manufacturing

< 1 MIN READ

Balancing on the Color Density Tightrope

May 26, 2015

By David Abercrombie Potential pitfalls and available solutions.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Rule Deck Comparison Doesn't Have to be Difficult

May 19, 2015

By Saunder Peng Comparing results from different rule decks can be frustrating. Learn how you can use a chip finishing...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Capacity Constraints and DFM at Mature Nodes

May 12, 2015

By Jeff Wilson, Mentor Graphics Design for manufacturing – it’s a variety of practices that can improve yield and prevent...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How to Use Pattern Matching to Improve Automatic Waiver Management

May 5, 2015

By John Ferguson and Jonathan Muirhead, Mentor Graphics Ensuring a known level of quality

By Calibre IC Design & Manufacturing

< 1 MIN READ

Migrating Consumer Electronics to the Automotive Market with Calibre PERC

April 28, 2015

By Matthew Hogan, Mentor Graphics Calibre PERC can help you succeed in the automotive market

By Calibre IC Design & Manufacturing

< 1 MIN READ

Cutting Fab Costs and Turnaround Time with Smart, Automated Resource Management

April 21, 2015

By Mark Simmons, Mentor Graphics Simple in theory, challenging in reality

By Calibre IC Design & Manufacturing

< 1 MIN READ

Free Is a Good Price, Especially for Process Design Kits

April 14, 2015

By Joseph Davis, Mentor Graphics The freePDK15 and its associated 15 nm Open Cell Library are now available!

By Calibre IC Design & Manufacturing

< 1 MIN READ

Accurate Lithography Simulation for Silicon Photonics

April 7, 2015

By Joe Kwan, Mentor Graphics Precise curved geometries are vital to making silicon photonics technology work

By Calibre IC Design & Manufacturing

< 1 MIN READ

Designing and Testing FinFet-based IC Designs

March 31, 2015

By Carey Robertson and Steve Pateras, Mentor Graphics Are your processes ready for finFETs?

By Calibre IC Design & Manufacturing

< 1 MIN READ

Self-Aligned Double Patterning, Part Deux

March 24, 2015

By David Abercrombie, Mentor Graphics Part 2 of a walk-through of the SADP process.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Auto IC Market: Revving Up Product Line Means Revving Up Reliability

March 17, 2015

By Matthew Hogan, Mentor Graphics Designing electronics for automotive use means meeting stringent safety and reliability standards.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Sign-off lithography simulation and multi-patterning must play well together

March 10, 2015

By Joe Kwan, Mentor Graphics At 20 nm and below, designers must ensure their lithography simulation can incorporate and analyze...

By Calibre IC Design & Manufacturing

< 1 MIN READ

2-5X Productivity Improvement in 14FDSOI Layout Design: STMicroelectronics Experience with Calibre RealTime

March 2, 2015

By Atul Bhargava and Mehak Malhotra, STMicroelectronics, India and Srinivas Velivala, Mentor Graphics Rather than just fixing DRC errors as...

By Calibre IC Design & Manufacturing

< 1 MIN READ

The Route to Faster Physical Verification and Better Designs

February 24, 2015

By Nancy Nguyen and Jean-Marie Brunet, Mentor Graphics Using the most accurate and up-to-date signoff engine instead of a limited...

By Calibre IC Design & Manufacturing

< 1 MIN READ

What about MEMS?

February 12, 2015

By Carey Robertson, Mentor Graphics With circuit performance driven by capacitance values, accurate calculations are critical for MEMs designers.

By Calibre IC Design & Manufacturing

< 1 MIN READ

A Look Behind the Mask of Multi-Patterning

January 28, 2015

By Michael White, Mentor Graphics An overview to the mystery of Multi-Patterning

By Calibre IC Design & Manufacturing

< 1 MIN READ

My Design's Interconnect Has Enough Wire Width to Withstand ESD... Doesn't It?

January 28, 2015

By Frank Feng, Mentor Graphics Electrostatic discharge can destroy a circuit, but designing adequate protection is not always a matter...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Self-Aligned Double Patterning, Part One

January 27, 2015

By David Abercrombie, Mentor Graphics A walk-through of the SADP process for success.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Are multi-patterning corners for parasitic extraction really necessary for 16/14 nm?

January 27, 2015

By Karen Chow, Mentor Graphics How does multi-patterning impact parasitic extraction? How many corners do you really need?

By Calibre IC Design & Manufacturing

< 1 MIN READ

How to Survive the Perfect Storm of Changing Fill Requirements

January 27, 2015

By Jeff Wilson, Mentor Graphics Using hierarchy in the fill process provides greater control for the designers, improves consistency throughout...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How shift-left memory contention analysis protects performance and schedule

Manufacturing Intelligence: AI in the Fab

Why curvilinear OPC demands a new optimization approach

From chaos to clarity: Smarter DRC workflows and team productivity with Calibre Vision AI

DRC at scale: How Calibre Vision AI turns billions of errors into actionable insights

Interactive symmetry checking with Calibre RealTime accelerates analog IC design

The Calibre 3D IC solution: Mastering the complexities of advanced 3D IC chip design

Tackling compute complexity in ESD verification with Calibre

Why a GPU rasterizer matters for computational lithography in both performance and precision at scale

Meeting the challenges of reliability verification for the era of 3D ICs

From data to domain expertise: How AI, accelerated computing and digital twins are reshaping semiconductor manufacturing

ICYMI: Siemens EDA at 2026 SPIE Advanced Lithography + Patterning

The engineering talent pipeline: How Siemens is helping to build tomorrow's workforce

How to use Calibre parasitic extraction tools: a step-by-step guide

Siemens acquires Canopus AI: Supercharging semiconductor manufacturing with AI-powered metrology

Calibre IC Manufacturing in 2025: The year’s biggest news

ESD verification in 3D ICs: Navigating unseen risks and new realities

Calibre IC Design in 2025: AI, 3D IC advancement and shift-left strategies drive verification excellence

Securing your silicon: Why automated IP integrity is non-negotiable in modern SoC design

6 frequent design rule checking errors every IC designer should know – and how Calibre nmDRC helps you avoid them

Bridging the gap: Unlock seamless collaboration in IC design with Calibre Connectivity Interface

The IC designers complete guide to design rule checking

IC visualization: Supercharge debug of hidden parasitic threats with Calibre

From translator to powerhouse: Calibre V2LVS second generation redefines LVS verification

Design rule checking in today’s integrated circuit design environment

Boost simulation results with powerful selective net extraction with Calibre xACT

Safeguarding IC reliability: Calibre PERC's latch-up guard ring check

Driving 3D IC innovation with Calibre multiphysics

Siemens-imec collaboration reduces stochastic failures in EUV lithography by orders of magnitude in wafer-level experimental validation

Enhancing IC Verification: Smarter solutions for faster, more reliable designs

Revolutionizing 3D IC design with integrated multiphysics verification

How to boost reliability with early-stage reliability checks

Navigating 3D IC stress: physical realities and best practices for 3D IC reliability

Ensure power domain compatibility by finding missing level shifters with Insight Analyzer

Stress less, innovate more: ensuring 3D IC reliability with Siemens Calibre 3DStress

Calibre Vision AI: a new era of fast, scalable chip-level DRC debug

Enhancing EUV lithography resolution at high numerical aperture

Overcoming noise challenges in analog and RF circuit design with Calibre PERC net shielding

Calibre xACT takes a hybrid approach to parasitic extraction

Smart strategies for metal fill extraction

Solving inter-domain leakage challenges: Enhancing IC design with Insight Analyzer

Smarter DRC for complex designs: Accelerating verification with Calibre nmDRC Recon

Easily manage multiple verification jobs with Calibre

Siemens shines at the 2025 SPIE Advanced Lithography + Patterning symposium

Solving IR drop and layout bottlenecks: How Calibre DesignEnhancer streamlines IC design

Transforming pre-layout IC reliability analysis with Siemens Insight Analyzer

Unlocking post-tapeout flow scalability and performance with cloud computing

Siemens EDA and TSMC partner to advance 3D IC Design

Shift left with Calibre interactive symmetry checking to improve design efficiency

Navigating ESD challenges in 2.5D/3D ICs: A guide to robust automated verification

An introduction to advanced verification techniques for IC design symmetry

Siemens Calibre 3DThermal wins 2024 WEAA award for innovation in 3D IC thermal analysis

Dr. Fedor Pikus cultivates engineering talent in Armenia

Shift left in IC design: A holistic strategy for faster, smarter verification

Tom Quan is now officially retired from TSMC

Enhanced short isolation process for faster circuit verification

Unveiling the future of 3DIC design with Calibre 3DThermal

Navigating the complex world of resistance extraction for curvilinear shapes in IC designs

Optimal ESD protection with Calibre PERC and Solido Simulation Suite

Cloud Flight Plans enable cost-effective use of the cloud for peak productivity

Faster design verification with Calibre nmLVS Recon Compare

Cracking the code: ensuring reliability and performance in IC design with EM/IR analysis

Shift left for more efficient block design and chip integration

Speeding up early design rule checking with Calibre nmDRC Recon

Automated analysis-based layout enhancements reduce power grid voltage drops during place & route: A case study with Google

Accelerate IP design cycles and reduce costs with Calibre design stage verification

Balancing performance vs. debuggability in LVS circuit verification

A new physical verification reporting solution smooths the on-time tapeout effort

How to verify well layer connectivity with soft checks

AI/ML rules at the 2024 SPIE Advanced Lithography + Patterning symposium

Unlocking the future with a digital twin for semiconductor manufacturing

Using a shift left strategy to address block/chip design challenges during design-stage verification

How to get accurate inductance extraction for superconductor ICs

The secret to Calibre software quality – AnaCov, our in-house code coverage analysis tool

Unraveling the 3DIC shift left strategy: Navigating the world of multi-dimensional ICs

Mastering parasitic extraction at the 3 nm process node

Why PID issues matter to IC chip designers, and how to combat them

Shifting left with Calibre solutions: Enhancing IP design flow efficiency and design quality

Revolutionizing software testing: Introducing TCP-Net++

Streamlining IC design verification with Calibre nmLVS Recon