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Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…

The “next” technology node: ready or not, here it comes

By Shelly Stalnaker For years, decades even, the semiconductor industry has lived by the process node, which was originally named…

Physical design engineers…Learn the secret to generating signoff fill in P&R and accelerating your tapeouts

By Srinivas Velivala Place and route (P&R) engineers are always on the lookout for ways to optimize their design flows…

IC package designers—looking for multi-die, system-level signoff verification?

By Shelly Stalnaker Ever tried a food sample when you were shopping…not just because it’s free food (!), but because…

Stronger together! Context-aware SPICE simulation combines the strengths of static and dynamic verification for faster, more precise full-chip ESD verification

By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…

Package verification just took a big step forward…

By Armen Asatryan and John Ferguson Over a decade ago, Calibre Design Solutions moved early into defining and building physical…

Coding for maximum performance and efficiency

A great software program does much, much more than just execute routines. It also optimizes the use of CPU resources…

Calibre Design Solutions takes a look back at 2021

Okay, is everyone ready for an end-of-year wrapup? It’s certainly been an eventful 2021 for Calibre Design Solutions, even if…

The most interesting man in EDA…

The most interesting man in EDA…

As the calendar year comes to a close, we face the prospect of saying goodbye to someone who has been…