Latest Posts

Give me my space! Why high voltage and multiple power domain designs need automated context-aware spacing checks

By Sherif Hany and Abdellah Bakhali Regardless of which technology node they’re using, design houses…

DFM: Still a really good thing to do!

By Simon Favre If you’re not using critical area analysis and design for manufacturing to…

Calibre and the Semiconductor Ecosystem

The Semiconductor Ecosystem- It is the definition of “High Tech”, but it isn’t just about…

Collaboration and innovation thrive on diversity

Back in November 2019, just a few short months before we all began an enforced…

What is critical area analysis and why should I care?

By Simon Favre What makes money in the semiconductor industry? A killer IC design? Something…

Adaptive Patterning: Moving with the times (and technologies)

By John Ferguson and Kevin Rinebold Deca Technologies’ Adaptive Patterning technology and their newly-announced adaptive…

Building a strong reliability foundation with Calibre PERC

By Matthew Hogan How are you handling your reliability verification right now? Custom reliability verification?…

Machine learning-enabled closed loop DFM

SPIE-ing at a distance…

The SPIE Advanced Lithography Digital Forum took place Feb 22-26, and of course, Siemens EDA…

Early circuit verification can get you to tapeout faster…here’s how

For the last few years, it’s been hard to see design teams struggling to meet…