Latest Posts

The path of least resistance…leads to more reliable designs

By Derong Yan Meeting tapeout schedules and performance requirements are equally critical conditions for IC design success. Now engineers can…

Extracting parasitics from MIM/MOM capacitors doesn’t have to hurt!

By Claudia Relyea and Sandeep Koranne  Analog/RF designers need both the speed of rule-based PEX, as well as the capacity…

Accelerating IC design time to market with Calibre in the cloud

By Michael White When you’re flying, it’s fun to look out the window and see clouds from “the other side.”…

Ease on down the road…why “ease of use” is the next big thing in EDA, and how we get there

Ease of use is an important issue when enhancing product functionality and introducing new technology. Calibre Design Systems considers ease…

DRC voltage text annotations: Manually placed texts can be wrong!

By Abdellah Bakhali System-on-chip (SoC) designs often use multiple intellectual property (IP) blocks from multiple IP providers. Each IP provider…

Do you trust the reliability of your 2.5D/3D IC package designs?

By Dina Medhat 2.5D/3D ICs have become an innovative solution for many design and integration challenges. Basic physical verification for…

Reliability checking for memory circuit design doesn’t have to destroy your eyesight!

By Hossam Sarhan Memory blocks contain sensitive analog circuits that are crucial for the proper functionality of the whole design….

DAC in December?? A Review of Calibre Design Solutions at DAC 2021

Did it feel a bit weird to be submitting research papers for DAC 2022 while packing to go to DAC…

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…