Latest Posts

Caution! Avoid detours when improving resistance on ESD paths

By Derong Yan As overall transistor dimensions shrink, integrated circuit (IC) chip designs become more sensitive to the damage caused…

Custom layout designers…Want to know a secret? You can close DRC faster. A lot faster…

By Srinivas Velivala Design rule checking (DRC) closure is a “tax” that custom layout designers must pay at all process…

So you think you know symmetry? Think again…

By Sherif Hany “The Art of Analog Layout” is one of the canonical books addressing concepts behind layout design techniques…

Can we just agree that perception is everything? Especially in IC design?

By Dennis Joseph Is the dress black and blue, or white and gold? Is that a rabbit or a duck?…

2.5/3D IC designers! Don’t get hung up on latch-up!

By Dina Medhat Latch-up is modeled as a short circuit (low-impedance path) that occurs in an integrated circuit (IC). It…

Don’t hit a roadblock in automotive electronics reliability verification!

The recent surge in used car prices may have you wondering what is driving this upswing, and just how much…

Efficient package delivery is not just for FedEx!

By John Ferguson Cost, risk, and the limitations of monolithic scaling are driving growth in multi-die (heterogeneous) advanced IC packaging…

Do you need an automated ESD verification methodology for 2.5D/3D ICs? If so, read on…

By Dina Medhat Electrostatic discharge (ESD) events cause severe damage to unprotected integrated circuits (ICs). You already know that, of…

P&R engineers! Interested in saving (LOTS of) time in your tapeout schedules?

By Srinivas Velivala As a P&R engineer, you probably spend lots of time 1) waiting for batch DRC runs to…