Latest Posts

Early circuit verification can get you to tapeout faster…here’s how

For the last few years, it’s been hard to see design teams struggling to meet…

Automated ESD protection verification for 2.5-3D ICs is now a reality

Got the mid-winter blahs? The post-New Year letdown? Looking for something to rev you up?…

Stochasticity of the input current is an important factor in accurate EM assessment for on-chip power delivery networks

At every conference, there is always that anticipatory moment just before the coveted “Best Paper”…

2021: Time to simplify your life (or at least your workload)?

Everyone makes resolutions for a better life at the start of a new year –…

Custom & digital layout designers…Use the Calibre RealTime Platform to close DRC fixes faster.

By Srinivas Velivala – Mentor, A Siemens Business Douglas Adams, who wrote The Hitchhiker’s Guide…

GLOBALFOUNDRIES and Mentor Launch a New Innovative DRC+ Hotspot Solution using Machine Learning in Calibre

By Shelly Stalnaker – Mentor, A Siemens Business I recently had the chance to attend…

LVS Zero to Hero in 3 Easy Steps

When it comes to system-on-chip (SoC) physical verification turnaround-time, layout vs. schematic (LVS) can make…

Mentor receives 2020 TSMC OIP Partner of the Year awards for EDA solutions

By Shelly Stalnaker – Mentor, A Siemens Business While the structure of the TSMC OIP…

Verification run configurations stressing you out? Automate them!

By Srinivas Velivala – Mentor, A Siemens Business As all new IC verification engineers learn…