Time is money…so why waste it on bad data?

By James Paris

Last Saturday was my son’s birthday and we had many things to do to get ready for his party. My first job of the day was to run to the store to pick up his cake and party supplies, so off to the store I rushed. I masked up, grabbed a cart, made my way to the bakery, and asked for his cake. It was then that I realized…I forgot my wallet! Arghhh! I’m sure we’ve all been there. Not the end of the world, but now I had to run home to get my wallet, drive back, and finish my shopping, which put me behind schedule. Had I paused for a second to check that I had my wallet before leaving home, I could have avoided the frustration and gotten everything done on time. Well, as they say, hindsight is 20/20.

As a chip integrator working in a parallel design flow, you likely see one common issue that has the same level of frustration. Ever run an overnight physical verification job only to find out the results are garbage because of mismatches between GDS IP and LEF abstracts? Those mismatches mean you and the rest of the team will get little to no value from the output—and what’s worse, now the project schedule is at risk. Why didn’t we check first? Well, I’m sure there are numerous responses…

  • They were the same the last time I ran PV, so they’re probably okay now.
  • Bob is always good about updating his abstracts, so I don’t need to check his.
  • Everyone knows the process and is responsible, so it’s their problem if it’s not correct.

Many times, the reason for the mismatches is as simple as not having an easy or reliable way to compare the two formats against each other. After all, they are very different, and comparing them is like comparing apples to oranges. But now, that’s just another excuse. The Calibre LEFDEF interface has an automated solution that can automatically compare common objects between LEF and GDS data and report any differences.

Adding a LEF versus GDS sanity check to your physical verification flow can help you avoid the frustration and schedule impact that out-of-sync design data can cause. If you’ve ever experienced this issue, you know what I’m talking about. To learn more about the Calibre LEFDEF interface, check out our paper, Data integrity checks save time and resources in parallel IC design flows. It won’t help you remember your wallet, but it can help you avoid wasting your time checking bad data.

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