Siemens shines at the 2025 SPIE Advanced Lithography + Patterning symposium

The SPIE Advanced Lithography + Pattering symposiums were held 23-27 February this year with the usual enthusiastic and sizable attendance (about 2200 people). The scientist at SPIE have fueled advancements in semiconductor manufacturing for 41 years. As always, the Calibre Manufacturing group was well represented with four invited papers and another 11 session papers covering topics like resolution enhancement for high-NA EUV lithography.

Siemens invited papers at SPIE

Our first invited paper, titled “A study on the improvement of machine leaning (ML)-based defect prediction model reflecting process variations” was presented by Seungsu Yoon of SAMSUNG Electronics on Feb 25. The paper was co-authored by Siemens engineers Kareem Madkour and Joe Kwan.

It focuses on the ability to predict and mitigate lithographic defects using an ML-Statistics Risk Pattern Predictor (ML-SRPP ). The ML-SRPP take a two-step approach:

1. Pattern segmentation and selection: The first step extracts the pattern type and usage of the product chip using a pattern segmentation technique. The Greedy algorithm is then employed to select the most representative patterns, providing a comprehensive understanding of the design landscape.
2. Unbiased variation estimation: To ensure the accuracy of the process variation data, the researchers applied an unbiased estimation method, ensuring 99% reliability. This robust data foundation is crucial for effectively predicting and mitigating potential defects that can negatively impact yield.

Our second invited paper, “Guided random synthetic layout generation and machine-learning based defect prediction for leading edge technology node development,” presented by Geng Han of IBM Thomas J. Watson Research Center on Feb 25. The paper was co-authored by Siemens engineers Joe Kwan, Sophie Rissberger, Qian Xie, Alex Dolgonos, Bennett Smith, Fan Jiang, Steven Lubin, Shibing Wang, Xuefeng Zeng and Yuyang Sun.

This paper presents a novel approach that combines synthetic layout generation (LSG) and machine-learning-based defect prediction (SONR) to drive faster development of new technology nodes for logic devices.

The key elements of the approach are:

• Limited ground rules: The approach starts with a limited set of ground rules for critical logic design, which serves as the foundation for the synthetic layout generation.
• Guided synthetic layouts: Using this limited design space, they create random yet guided synthetic layout (LSG) patterns. These patterns complement existing functional and OPCV macros, providing a rich testbed for defect identification.
• Targeted defect inspection: By focusing SEM inspection on these LSG patterns, they can identify multiple types of process hotspots in a concentrated region, significantly improving the defect inspection efficiency.
• Calibrated defect models: The silicon results from the LSG patterns are then used to calibrate the Calibre SONR defect models, ensuring accurate prediction of potential issues.
• Accelerated root cause analysis: Hotspot analysis based on process and design-related features allows us to quickly identify the root causes of the observed defects.
• Iterative process refinement: These insights can then be used to refine the lithography, etch, and CMP processes, and/or update specific design rules, thereby accelerating the overall process node development and yield ramp.

By combining the power of synthetic layout generation and machine-learning-driven defect prediction, our approach enables a more efficient and targeted path to new technology node development, with the potential to significantly reduce time-to-market and improve yield.

On Feb 26, David Power of TEL Technology center presented the invited paper “A comparison of SALELE with traditional lithography and anti-spacer technology.” The co-authors from Siemens are Xuefeng Zeng, Alex Wei and Yuyang Sun.

Advanced patterning solutions have been the driving force behind continuous scaling in semiconductor technology, even as the industry has grappled with delays in the introduction of next-generation lithography wavelengths and techniques. Two such solutions, self-aligned double patterning (SADP) and self-aligned litho-etch-litho-etch (SALELE), leveraged the ability to self-align features to enable further scaling. However, these techniques come with a trade-off – the deposition and etching of multiple materials, which can reduce throughput and increase manufacturing costs compared to direct feature printing.

In this work, they present a compelling alternative: anti-spacer technology. This approach enables both self-aligned pitch splitting and high throughput through a single-pass, track-based process. By utilizing anti-spacer technology for lithography, they achieve a significant reduction in the initial litho CD, reaching a quarter of the design pitch, compared to only half the design pitch with traditional lithography.

The improved CD uniformity, line edge roughness, and stochastic effects translate to a substantial reduction in defectivity. They delve into the details of this process, starting with layout decomposition, where the drawn layer is split into four masks: two metal-like masks and two block-like masks. Each of these masks then undergoes a tailored Optical Proximity Correction (OPC) process, which they explore in depth.

Finally, they compare the two processes – traditional SALELE and the anti-spacer SALELE approach – in terms of variation and edge placement error (EPE) verification, showcasing the advantages of the anti-spacer technology.

By unlocking the power of anti-spacer technology, they have pushed the boundaries of patterning, delivering a solution that not only enables continued scaling but also enhances throughput and yield. This work represents a significant step forward in the quest to overcome the challenges facing the semiconductor industry, paving the way for even greater advancements in the years to come.

The fourth invited paper from Siemen and our research partners at imec and Lam Research, was presented on Feb 27 by Dongbo Xu of Siemens EDA. Titled “OPC model accuracy of dry resist readiness for 0.55NA EUVL by using low-n bright field mask,”covers the challengesthe semiconductor industry faces as it prepared to embrace High Numerical Aperture Extreme Ultraviolet Lithography (0.55NA EUVL). The importance of advanced materials and patterning techniques has never been more critical. Resolution, roughness, defectivity and process window are all key considerations as we push the boundaries of what’s possible.

Among the various combinations of mask absorber materials, mask tones, and processes, bright field (BF) masks utilizing negative-tone metal oxide resists (MORs) have emerged as one of the most promising candidates for 0.55NA EUVL patterning. Lam Research has taken this a step further by developing a novel flow that incorporates dry resist deposition and dry resist development.

This new process brings a unique set of advantages and specificities that demonstrate impressive patterning performance on 0.55NA EUVL. However, this advancement also has implications for the OPC flow, which must be carefully evaluated.

In this paper, they investigate the accuracy of the Calibre OPC model for the dry resist process, using a low-n attenuated phase-shift BF mask. The use case is based on the imec N2 (pitch 28nm) metal design, with wafer exposure performed on the imec NXE 3400 scanner.

By unlocking the potential of dry resist processes for high-NA EUV lithography, they are paving the way for continued advancements in semiconductor manufacturing.

Siemens papers at SPIE

The 12 other papers delved into a variety of topics like resolution enhancement for high-NA EUV lithography, enabling 0.55NA EUV bright field mask stitching, using AI/ML to improve process defect prediction accuracy, optimizing EUV OPC runtimes, ML-based etch retargeting, a novel ML and image processing solution, metrology for anti-spacer, AI-based clustering and SEM contour, e-beam and EUV model variability and using ML clustering to optimize OPC models.

For more details on the papers we presented, plus additional resources, visit Calibre IC Manufacturing papers at SPIE 2025.

The Nick Cobb memorial scholarship

Siemens EDA also partnered with SPIE to present the annual Nick Cobb Memorial Scholarship to Mr. Clay Klein, a PhD student in physics at JILA and the University of Colorado, Boulder.

YuYang Sun, the Vice President of Siemens EDA’s Calibre Manufacturing Solutions, said, “The scholarship honors Nick’s pioneering work in the field of lithography and his significant contributions as the chief architect of Siemens Calibre OPC solutions. It is particularly noteworthy that Clay is pursuing his PhD at the same school where Nick completed his undergraduate education, the University of Colorado at Boulder. We are proud to continue this legacy of fostering innovation and engineering talent, especially as Clay’s research on EUV metrology is highly relevant to addressing our industry’s challenges at advanced nodes.”

Other notable events at SPIE included a tribute to industry icon Bob Dennard, who died last year at age 91. Dennard invented the single transistor DRAM and devised the physics that allows for continued scaling, known as “Dennard scaling.”

If you’re interested in learning more about our work in any of these fields, let us know! Call us at 1-800-547-3000, or send us a note telling us what topics you’d like more information about.