By Dina Medhat – Mentor, A Siemens Business
Design rule waivers
Maybe a design rule that made sense at 22nm just doesn’t apply at 10nm, but it’s still in the rule deck. Or the foundry decides that a spacing error will have an insignificant effect on manufacturability, but it’s still part of the signoff checks. For reasons like these and many others, there are always some DRC errors that just don’t matter. Spending any time reviewing and debugging these errors is time that could be better spent debugging errors that really do impact manufacturability or performance.
With an eye to efficiency, design companies and foundries have long worked together to identify and “waive” these trivial errors, meaning they can be disregarded during debugging. EDA companies stepped up with automated waiver processes that let design teams mark the waived errors so that they could be automatically identified and set aside during the review process.
That worked well for DRC waivers, but in today’s designs, designers also have to apply reliability checks that combine topological and geometrical information, such as ESD and latch-up protection, multi-power domain crossing checks, and voltage-aware DRC. Those checks don’t fit neatly into standard automated waiver solutions, meaning a new approach is needed.
LDL-DRC, P2P resistance, and CD check waivers
At Mentor, a Siemens business, we enhanced our Calibre PERC reliability platform with customized waivers management functionality that can process logic-driven layout DRC results, as well as point-to-point parasitic resistance and current density check errors. Calibre PERC automated waivers processing is supported at both the IP and full-chip level. Designers can choose to apply default waiving criteria, or easily define customized waiving criteria as needed to support their company’s best practices for reliability design. Of course, just like its DRC counterpart, the automated reliability check waivers flow saves all the waived results in a separate database for future reference.