Calibre PERC

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SAFE is good. SAFE awards are even better…

June 1, 2021

By Calibre staff Safe is good, right? We all want to be safe, especially these days. But safe took on…

By Design With Calibre
2 MIN READ

Building a strong reliability foundation with Calibre PERC

March 9, 2021

By Matthew Hogan How are you handling your reliability verification right now? Custom reliability verification? No reliability verification? How confident…

By Design With Calibre
3 MIN READ

Automated ESD protection verification for 2.5-3D ICs is now a reality

January 28, 2021

Got the mid-winter blahs? The post-New Year letdown? Looking for something to rev you up? How about an automated method…

By Design With Calibre
2 MIN READ

Do you have a reliable automated waiver process for reliability verification?

October 13, 2020

By Dina Medhat – Mentor, A Siemens Business Design rule waivers Maybe a design rule that made sense at 22nm…

By Design With Calibre
2 MIN READ
Automated Power Model Verification for Analog IPs

Automated Power Model Verification for Analog IPs

February 23, 2016

By Sierene Aymen and Hartmut Marquardt, Mentor Graphics Eliminating manual work during power intent verification of analog IPs reduces susceptibility…

By Design With Calibre
4 MIN READ
An Automated Solution for Voltage-Aware DRC

An Automated Solution for Voltage-Aware DRC

February 2, 2016

By Dina Medhat, Mentor Graphics Automated voltage propagation with Calibre PERC makes it easier to comply with voltage-aware DRC spacing…

By Design With Calibre
4 MIN READ
Electromigration and IC Reliability Risk

Electromigration and IC Reliability Risk

January 19, 2016

By Dina Medhat, Mentor Graphics Gradual damage from electromigration can affect product performance and reduce product lifetimes. Reliability analysis ensures…

By Design With Calibre
5 MIN READ
LEF/DEF IO Ring Check Automation

LEF/DEF IO Ring Check Automation

December 15, 2015

By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings…  

By Design With Calibre
5 MIN READ
Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

November 3, 2015

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks on multiple-power-domain and mixed-signal designs…

By Design With Calibre
4 MIN READ