2021: Time to simplify your life (or at least your workload)?

Everyone makes resolutions for a better life at the start of a new year –…

Custom & digital layout designers…Use the Calibre RealTime Platform to close DRC fixes faster.

By Srinivas Velivala – Mentor, A Siemens Business Douglas Adams, who wrote The Hitchhiker’s Guide…

Verification run configurations stressing you out? Automate them!

By Srinivas Velivala – Mentor, A Siemens Business As all new IC verification engineers learn…

SAFE at home! Attending the Samsung SAFE forum in 2020

By Shelly Stalnaker – Mentor, A Siemens Business Samsung is going virtual with their 2020…

Do you have a reliable automated waiver process for reliability verification?

By Dina Medhat – Mentor, A Siemens Business Design rule waivers Maybe a design rule…

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs….

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation…

Design Rule Checking for Silicon Photonics

By Ruping Cao, Mentor Graphics Verifying silicon photonics designs requires new techniques, like equation-based DRC…

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks…