Design Rule Checking for Silicon Photonics

By Ruping Cao, Mentor Graphics Verifying silicon photonics designs requires new techniques, like equation-based DRC…

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks…

Managing Waivers Throughout the Custom Design Lifecycle

By Srinivas Velivala, Mentor Graphics Custom designer? Learn how you can easily manage DRC waivers…

Custom Layout Designers Need New Tools for New and Expanding Markets

By Srinivas Velivala, Mentor Graphics New debugging capabilities in Calibre RealTime can help shrink your…

Rule Deck Comparison Doesn’t Have to be Difficult

By Saunder Peng Comparing results from different rule decks can be frustrating. Learn how you…

How to Use Pattern Matching to Improve Automatic Waiver Management

By John Ferguson and Jonathan Muirhead, Mentor Graphics Ensuring a known level of quality…

2-5X Productivity Improvement in 14FDSOI Layout Design: STMicroelectronics Experience with Calibre RealTime

By Atul Bhargava and Mehak Malhotra, STMicroelectronics, India and Srinivas Velivala, Mentor Graphics Rather than…

The Route to Faster Physical Verification and Better Designs

By Nancy Nguyen and Jean-Marie Brunet, Mentor Graphics Using the most accurate and up-to-date signoff…