DRC

Filter by:
Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

January 16, 2017

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs.

By Design With Calibre
< 1 MIN READ
Transistor level ESD verification in large SoC designs

Transistor level ESD verification in large SoC designs

October 31, 2016

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help

By Design With Calibre
4 MIN READ
Design Rule Checking for Silicon Photonics

Design Rule Checking for Silicon Photonics

November 17, 2015

By Ruping Cao, Mentor Graphics Verifying silicon photonics designs requires new techniques, like equation-based DRC

By Design With Calibre
9 MIN READ
Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

November 3, 2015

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks on multiple-power-domain and mixed-signal designs…

By Design With Calibre
4 MIN READ
Custom Layout Designers Need New Tools for New and Expanding Markets

Custom Layout Designers Need New Tools for New and Expanding Markets

July 1, 2015

By Srinivas Velivala, Mentor Graphics New debugging capabilities in Calibre RealTime can help shrink your time-to-tapeout while still ensuring high-quality…

By Design With Calibre
4 MIN READ
Rule Deck Comparison Doesn’t Have to be Difficult

Rule Deck Comparison Doesn’t Have to be Difficult

May 19, 2015

By Saunder Peng Comparing results from different rule decks can be frustrating. Learn how you can use a chip finishing…

By Design With Calibre
5 MIN READ
How to Use Pattern Matching to Improve Automatic Waiver Management

How to Use Pattern Matching to Improve Automatic Waiver Management

May 5, 2015

By John Ferguson and Jonathan Muirhead, Mentor Graphics Ensuring a known level of quality

By Design With Calibre
6 MIN READ
2-5X Productivity Improvement in 14FDSOI Layout Design: STMicroelectronics Experience with Calibre RealTime

2-5X Productivity Improvement in 14FDSOI Layout Design: STMicroelectronics Experience with Calibre RealTime

March 2, 2015

By Atul Bhargava and Mehak Malhotra, STMicroelectronics, India and Srinivas Velivala, Mentor Graphics Rather than just fixing DRC errors as…

By Design With Calibre
6 MIN READ
The Route to Faster Physical Verification and Better Designs

The Route to Faster Physical Verification and Better Designs

February 24, 2015

By Nancy Nguyen and Jean-Marie Brunet, Mentor Graphics Using the most accurate and up-to-date signoff engine instead of a limited…

By Design With Calibre
4 MIN READ