By John Ferguson IC design’s evolution continues to push the boundaries of Moore’s law to new heights. One of the…
By Derong Yan Integrated circuit (IC) chip designers are constantly striving to meet ever-increasing standards of reliability and performance in…
By Abdellah Bakhali If you’re not an electrostatic discharge (ESD) expert (and let’s face it, most of us aren’t), verifying…
By Slava Zhuchenya So your net trace has too much parasitic resistance. Where is it coming from? You ran your…
By Dina Medhat 2.5D/3D ICs have become an innovative solution for many design and integration challenges. Basic physical verification for…
By Hossam Sarhan Memory blocks contain sensitive analog circuits that are crucial for the proper functionality of the whole design….
Did it feel a bit weird to be submitting research papers for DAC 2022 while packing to go to DAC…
By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…
By Matthew Hogan and Derong Yan As we all know, during the final sign-off verifications of full chip system-on-chip (SoC)…
