Find high resistance faster in P2P violations with interactive P2P analysis

By Slava Zhuchenya So your net trace has too much parasitic resistance. Where is it coming from? You ran your…

Do you trust the reliability of your 2.5D/3D IC package designs?

By Dina Medhat 2.5D/3D ICs have become an innovative solution for many design and integration challenges. Basic physical verification for…

Reliability checking for memory circuit design doesn’t have to destroy your eyesight!

By Hossam Sarhan Memory blocks contain sensitive analog circuits that are crucial for the proper functionality of the whole design….

DAC in December?? A Review of Calibre Design Solutions at DAC 2021

Did it feel a bit weird to be submitting research papers for DAC 2022 while packing to go to DAC…

Stronger together! Context-aware SPICE simulation combines the strengths of static and dynamic verification for faster, more precise full-chip ESD verification

By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…

Cloud Computing Makes Overnight TAT Attainable

By Matthew Hogan and Derong Yan As we all know, during the final sign-off verifications of full chip system-on-chip (SoC)…

Don’t hit a roadblock in automotive electronics reliability verification!

The recent surge in used car prices may have you wondering what is driving this upswing, and just how much…

Turn IC verification challenge from a hard slog into a walk in the park by using static checks

By Neel Natekar As integrated circuits (ICs) grow in complexity, they create new challenges for IC verification flows and electronic…

Building a strong reliability foundation with Calibre PERC

By Matthew Hogan How are you handling your reliability verification right now? Custom reliability verification? No reliability verification? How confident…