You’re integrating your design. Some blocks are incomplete. Others just have placeholders. But you can’t wait until every component is finished, because your schedule doesn’t wait. So you start circuit verification, only to find yourself slogging through hundreds, maybe even thousands, of errors, most of which you know are going to turn out to be caused by the incomplete state of your design. But what else can you do? You can’t risk leaving a real short in the layout, can you?
What if there was a faster, smarter way to get through that early-stage verification by focusing only on the high-impact errors, like shorts? And what if you could divide up your design, maybe by layers, or nets, so different people could be debugging the design simultaneously?
Our innovative Calibre nmLVS-Recon tool provides focused verification technologies that enable design teams to rapidly examine dirty, incomplete, and immature designs to find and fix selective high-impact circuit errors earlier and faster, without modifying the foundry rule deck.
To help you understand how this targeted early-design verification can help you shave significant time off your tapeout schedules, our latest video introduces the Calibre nmLVS-Recon short isolation use model, and explains how you can use it to methodically find and quickly fix selected shorts errors during early design integration stages. Database reuse speeds up execution, while on-the fly debugging and resolution of shorts lets you quickly verify your fixes. With the Calibre nmLVS-Recon tool, you can now prioritize high-value early-stage verification strategies to shorten your debug cycle and deliver designs on schedule.
Fifteen minutes to save hours, maybe even days, in your tapeout schedules? Grab a cup of coffee, hit the play button, and you could be on your way to faster, more efficient early design verification.