Introducing Calibre DesignEnhancer design-stage layout optimization!

By Jeff Wilson

At the Design Automation Conference (DAC) last week, Calibre Design Solutions introduced the Calibre DesignEnhancer tool, our newest addition to the Calibre nmPlatform toolsuite. The Calibre DesignEnhancer tool is part of a growing suite of shift left tools within the Calibre nmPlatform designed to support the earlier application of design physical verification and optimization to help design teams achieve their PPA goals faster, and with Calibre confidence.

The Calibre DesignEnhancer tool offers P&R and custom/analog design teams a fast, integrated environment for implementing Calibre-clean design modifications to reduce IR drop and EM issues and shorten time to market. The Calibre DesignEnhancer tool currently offers three use models:

• Via insertion to reduce IR drop on user-specified nets. By using detailed knowledge of the design rules and connectivity, the Calibre DesignEnhancer Via use model maximizes the via insertion rate, and can be used by both IP and SOC designers.
• Parallel run lengths insertion to reduce IR drop issues on the power grid. Adding both metal interconnect and vias in white space or open tracks to create parallel paths reduces resistance. Designers can focus the insertions on specific areas of the layout to achieve maximum reduction in IR drop in the areas where it is most needed, while limiting the impact on timing.
• Filler/DCAP cell insertion to insert DCAPs, ECO DCAPs, and filler cells to the P&R design after the logic is placed. This use model is significantly faster than P&R flows, so designs are ready for physical verification in far less time. In addition, designers can establish density targets for the insertion of the DCAP and ECO DCAP cells, enabling teams to better address dynamic IR drop by controlling the location and amount of these DCAP cells in the layout.

At a luncheon event on Tuesday, I had the opportunity to introduce the Calibre DesignEnhancer tool and its functionalities, and then speakers from Juniper Networks and Intel discussed their results using the Calibre DesignEnhancer use models on production designs. Later in the day, I visited the Samsung booth to share details of how Siemens and Samsung collaborated to develop solutions based on Calibre DesignEnhancer use models.

Interested in learning more about the Calibre DesignEnhancer tool, and the significant gains you can achieve in productivity and design quality? Visit the Calibre DesignEnhancer product page on the Siemens EDA website for more details and resources, or contact your Calibre representative.