By James Paris
We’ve all played those “Spot the Difference” games where you look at two similar images and try to find all the changes from the first to the second. More often than not, you can find most of the differences relatively quickly, but then spend a loooong time trying to find those last few elusive disparities. While this sort of mind-teaser can be a fun way to spend some free time, data comparison in an integrated circuit design implementation flow is definitely no game, and it’s certainly not a place where missing a few differences is acceptable.
Fortunately, for mask-level layout vs. layout (LVL) comparisons, applications like Calibre nmDRC design rule checking can use the Calibre FastXOR solution for thorough, accurate database comparisons. Of course, second only to accuracy is performance. Because the Calibre FastXOR application is also, well, fast (and efficient), you can run mask LVL comparisons many times a day, from the first block to final full-chip tapeout, helping you find and eliminate issues before they become gnarly, time-consuming obstacles at tapeout.
However, to ensure you’re getting the best performance that the Calibre FastXOR application has to offer, there are some suggested best practices for rule deck optimizations before you start. Our technical paper Optimize layout vs. layout design comparisons for faster runtimes provides a detailed guide, along with insights into how you can further optimize the Calibre FastXOR solution to ensure the fastest overall performance with every run.