Give me my space! Why high voltage and multiple power domain designs need automated context-aware spacing checks

By Sherif Hany and Abdellah Bakhali Regardless of which technology node they’re using, design houses that create high-voltage and multiple…

2021: Time to simplify your life (or at least your workload)?

Everyone makes resolutions for a better life at the start of a new year – why not resolve to make…

Verification run configurations stressing you out? Automate them!

By Srinivas Velivala – Mentor, A Siemens Business As all new IC verification engineers learn very quickly, there is far…

A touchy subject: RF IC layout verification

By Neel Natekar – Mentor, A Siemens Business Radio frequency (RF) circuitry is an essential component of many of the…

How to run Calibre PERC jobs using Calibre Interactive

How to run Calibre PERC jobs using Calibre Interactive

Running Calibre PERC jobs from the Calibre Interactive interface tool only requires a few easy steps. Get the details in…

A new path for analog design constraints verification

A new path for analog design constraints verification

By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for reliability and performance.

Transistor level ESD verification in large SoC designs

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help

Context-Aware Latch-up Checking

Context-Aware Latch-up Checking

By Matthew Hogan, Mentor Graphics Latch-up detection is challenging. Learn how automated LUP checks help you find and eliminate LUP…

Leveraging Reliability-Focused Foundry Rule Decks

Leveraging Reliability-Focused Foundry Rule Decks

By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you correct reliability issues while they…