Transistor level ESD verification in large SoC designs

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help

Context-Aware Latch-up Checking

Context-Aware Latch-up Checking

By Matthew Hogan, Mentor Graphics Latch-up detection is challenging. Learn how automated LUP checks help you find and eliminate LUP…

Leveraging Reliability-Focused Foundry Rule Decks

Leveraging Reliability-Focused Foundry Rule Decks

By Matthew Hogan, Mentor Graphics Using your foundry‚Äôs reliability rule deck early on lets you correct reliability issues while they…

Reliability Scoring for the Automotive Market

Reliability Scoring for the Automotive Market

By Jeff Wilson, Mentor Graphics Companies designing automotive electronics must understand how variability affects design quality and reliability.

Interconnect Robustness Depends on Scaling for Reliability Analysis

Interconnect Robustness Depends on Scaling for Reliability Analysis

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…

Electrical Overstress Detection and Debugging

Electrical Overstress Detection and Debugging

By Dina Medhat, Mentor Graphics Automated voltage propagation provides an accurate way to detect and correct those hard-to-find EOS conditions…

The Changing (and Challenging) IC Reliability Landscape

The Changing (and Challenging) IC Reliability Landscape

By Matthew Hogan, Mentor Graphics Reliability issues have gone way beyond DRC and LVS verification…